AK8140A Datasheet, PDF (15/45 Pages) Asahi Kasei Microsystems – Programmable Clock Generator

Function Description
AK8140A
 Power up sequence
Step1 : Supplying proper voltage to the power pins with PD_N pin =”L”.
*Note: VDD1-4 must be supplied simultaneously.
The assumption power start time to reach 90 % of VDD is within 20 ms.
Step2 : Set the PD_N pin to “H”1 second after the point that the power supply reaches 90% of VDD.
Step3 : SCL / SDA are acceptable min 2ms later.
VDD1-4
PD_N
90% of VDD1-4
Max 20ms
Min 1s
SDA / SCL
Min 2ms
SDA / SCL input acceptable
CLK1-3
CLK4p
CLK4n
draft-E-06
- 15 -
Sep -12