AK8140A Datasheet, PDF (19/45 Pages) Asahi Kasei Microsystems – Programmable Clock Generator

AK8140A
●Register Configuration
AK8140A has Register can be programmed via the serial SDA/SCL interface.
The following tables and explanations describe the programmable functions of Ak8140A.
・Default register state is all ‘0’.
The default setting appears after power is supplied or after power-down/up sequence until it
is reprogrammed to a different setting.
・All data transferred with the MSB first.
・When a Certain Setting is set by two or more Address, please write the data to all Address.
・Write ‘0’ to Reserved bits.
Address
Offset
00h
20h
30h
Table AK8140A Register Configuration
Register
Generic Configuration
Register
PLL1 Configuration
Register
PLL2 Configuration
Register
Remarks
Page
Device Setting
・Device Setting (S0/S1/S2)
for Serial Programming mode
・Device Input clock(Crystal or Ext-in)
・Slave Address A1
p.21
CLK1 to 4 Setting
・CLK1 to 4 Output State
（CLK enabled / Disabled to L /Disabled to H /
Hi-Z）
・MUX1 to 4
(PLL1 fVCO1/ PLL2 fVCO2/ Input Bypass)
・ODIV1 to 4 Parameter
・CLK1 to 4 Output Buffer Drivability
・CLK4 Output Level LVDS or CMOS
PLL1 Setting
p.33
（Input CLK of PLL1,
MDIV1, NDIV1, fVCO1 range）
PLL2 Setting
p.39
（MDIV2,NDIV2,fVCO2 range）
draft-E-06
- 19 -
Sep -12