AK8140A Datasheet, PDF (7/45 Pages) Asahi Kasei Microsystems – Programmable Clock Generator

AK8140A
over VDD1-4: 3.0 to 3.6V, VDDO1-2:1.7 to 3.6V, Ta: -40 to +85℃, unless otherwise noted
Parameter
PLL1 Characteristics
VCO frequency1
Symbol
Conditions
MIN TYP MAX
fVCO1
VCO frequency range of
PLL1
230
460
Unit
MHz
Phase Comparison Frequency1 fcmp1
Period Jitter1 ^{(1)(2)(3)(4)(7)}
Jit_period
Cycle to Cycle Jitter1^{(1)(2)(3)(5)(7)}
Jit_C2C
Long Term Jitter1^{(1)(2)(3)(6)(7)}
PLL2 Characteristics
VCO frequency2
Jit_long
fVCO2
6.75
13.5
Jitter of Output clock from
PLL1
8.3
1
Jitter of Output clock from
PLL1
12.8
1
Jitter of Output clock from
PLL1
40
1000 cycle delay, 1
VCO frequency range of
PLL2
80
230
MHz
ps
ps
ps
MHz
Phase Comparison Frequency2 fcmp2
2.5
14.375 MHz
Period Jitter2 ^{(1)(2)(3)(4)(7)}
Jit_period
Jitter of Output clock from
PLL2
1
8.3
ps
Cycle to Cycle Jitter2^{(1)(2)(3)(5)(7)}
Jit_C2C
Jitter of Output clock from
PLL2
1
12.8
ps
Long Term Jitter2^{(1)(2)(3)(6)(7)}
Jit_long
Jitter of Output clock from
PLL2
1000 cycle delay, 1
41.7
ps
Note
(1) Design Value
(2) With the load describes on page5.
(3) When only one side is taking out operation or the same frequency among the output buffers which share a power
supply pin (VDDO1, 2).
(4) Jitter depends on configuration. Jitter data is for input frequency = 48MHz, output frequency = 27M/48M/50MHz.
(5) Jitter depends on configuration. Jitter data is for input frequency = 25M/30M/50MHz,
output frequency = 27M/50MHz.
(6) Jitter depends on configuration. Jitter data is for input frequency = 27MHz, output frequency = 25M/148.5MHz.
(7) 10000 sampling or more
draft-E-06
-7-
Sep -12