AK8140A Datasheet, PDF (12/45 Pages) Asahi Kasei Microsystems – Programmable Clock Generator

AK8140A
-PLL2 Setting Procedure-
Output frequency from PLL2 is determined by PLL2 parameter: REFCLK Dividing value (MDIV2),
Fractional-N2 Dividing value (INT, FRAC), and OUTPUT Dividing value (ODIV1-4).
These parameters should be set as described below.
fin2
MDIV2 _{fcmp2 PFD/CP/LPF/}
fvco2
foutn
ODIVn
NDIV2
VCO
(INT+FRAC)
Figure.6 PLL2 Block Diagram
Step1. Deciding VCO2 target frequency.
This frequency (fvco2) is decided from CLKn Output frequency (foutn) and Output dividing value
(ODIVn, set by address: 0Dh~13h). Set fVCO2 frequency between 80MHz to 230MHz.
Where
80MHz≦fVCO2≦230MHz (fVCO2=foutn×ODIVn)
Step2. Deciding MDIV2 and NDIV2 value when PLL2 is assumed to be Integer PLL.
Set MDIV2 and NDIV2 divider as fcmp2 becomes the highest common measure of fin2 and fvco2.
Where
6.75MHz≦fcmp2≦13.5MHz
MDIV2 (M2):1 to 511
NDIV2 (N2): 1 to 4095
M2 ≦ N2
(fcmp2= fin2 / MDIV2)
Step3. Calculating MDIV2 and NDIV2 values of fractional-N PLL.
Calculate the dividing value of fractional divider, as follows.
MDIV 2  2^P
NDIV 2

N _INT

N _NUME
N _DENO
P

4

int


log
2
N2
M2


*{if P < 0 then P = 0}
N _INT
 int_{}
N2 2^P
M2

N_NUME  N 2  2^P  M 2  N_INT
N_DENO  M 2
Sep -12
- 12 -
draft-E-06