AK8140A Datasheet, PDF (26/45 Pages) Asahi Kasei Microsystems – Programmable Clock Generator

AK8140A
●Address：04h～0Bh
Data
Address
D7
D6
D5
D4
D3
D2
D1
D0
CLK1_0 CLK1_0 CLK1_1 CLK1_1 CLK1_2 CLK1_2 CLK1_3 CLK1_3
04h
ï¼»1]
ï¼»0]
ï¼»1]
ï¼»0]
ï¼»1]
ï¼»0]
ï¼»1]
ï¼»0]
CLK1_4 CLK1_4 CLK1_5 CLK1_5 CLK1_6 CLK1_6 CLK1_7 CLK1_7
05h
ï¼»1]
ï¼»0]
ï¼»1]
ï¼»0]
ï¼»1]
ï¼»0]
ï¼»1]
ï¼»0]
CLK2_0 CLK2_0 CLK2_1 CLK2_1 CLK2_2 CLK2_2 CLK2_3 CLK2_3
06h
ï¼»1]
ï¼»0]
ï¼»1]
ï¼»0]
ï¼»1]
ï¼»0]
ï¼»1]
ï¼»0]
CLK2_4 CLK2_4 CLK2_5 CLK2_5 CLK2_6 CLK2_6 CLK2_7 CLK2_7
07h
ï¼»1]
ï¼»0]
ï¼»1]
ï¼»0]
ï¼»1]
ï¼»0]
ï¼»1]
ï¼»0]
CLK3_0 CLK3_0 CLK3_1 CLK3_1 CLK3_2 CLK3_2 CLK3_3 CLK3_3
08h
ï¼»1]
ï¼»0]
ï¼»1]
ï¼»0]
ï¼»1]
ï¼»0]
ï¼»1]
ï¼»0]
CLK3_4 CLK3_4 CLK3_5 CLK3_5 CLK3_6 CLK3_6 CLK3_7 CLK3_7
09h
ï¼»1]
ï¼»0]
ï¼»1]
ï¼»0]
ï¼»1]
ï¼»0]
ï¼»1]
ï¼»0]
CLK4_0 CLK4_0 CLK4_1 CLK4_1 CLK4_2 CLK4_2 CLK4_3 CLK4_3
0Ah
ï¼»1]
ï¼»0]
ï¼»1]
ï¼»0]
ï¼»1]
ï¼»0]
ï¼»1]
ï¼»0]
CLK4_4 CLK4_4 CLK4_5 CLK4_5 CLK4_6 CLK4_6 CLK4_7 CLK4_7
0Bh
ï¼»1]
ï¼»0]
ï¼»1]
ï¼»0]
ï¼»1]
ï¼»0]
ï¼»1]
ï¼»0]
CLKn_x [1:0] ： CLK1～4 Output State Definition
CLKn_x [1:0] bit set output state(CLKn_x) defined in the table on page 15 can be set up.
The output frequency at the time CLKn_x is set to “CLK Enabled” (CLKn_x[1:0] ='00')
follows MUXn/ODIVn setting.
* ODIVn function is stopped, when CLKn state is set to Disable (CLKn_x[1:0]
='01'/'10'/'11').
* When CLK4 state is set to Disable, CLK4p/4n each pin will be the following state.
CLK4_x[1:0]＝‘01’/‘10’/‘11’：CLK4ｐ/4n ＝ ‘L’/‘L’，‘H’/‘H’，‘Hi-Z’/‘Hi-Z
CLKn_x [1:0]
00
01
10
11
CLKn Output State
CLK Enabled
Disable to Low
Disable to High
Disable to Hi-z
(n=1～4、x=0～7)
Sep -12
- 26 -
draft-E-06