AK8140A Datasheet, PDF (37/45 Pages) Asahi Kasei Microsystems – Programmable Clock Generator

AK8140A
 PLL2 Configuration Register
Address
30h
D7
FS2_0
0
D6
FS2_1
0
D5
FS2_2
0
Data
D4
D3
FS2_3 FS2_4
0
0
D2
FS2_5
0
D1
FS2_6
0
D0
FS2_7
0
Remarks
PLL2 Frequency
Selection
31h
Reserved
0
Reserved
0
MDIV0[2]
0
MDIV0[1]
0
MDIV0[0]
0
VCO2_RA VCO2_RA
NGE0[1] NGE0[0]
0
0
Reserved
0
PLL2_0
MDIV2Setting
fVCO2 Range
32h
NINT0[5]
0
NINT0[4]
0
NINT0[3]
0
NINT0[2]
0
NINT0[1]
0
NINT0[0]
0
NUME0[8] NUME0[7]
0
0
33h
NUME0[6]
0
NUME0[5]
0
NUME0[4]
0
NUME0[3]
0
NUME0[2]
0
NUME0[1]
0
NUME0[0]
0
DENO0[8]
0
PLL2_0
NDIV2 Setting
34h
35h
36h
37h
DENO0[7] DENO0[6] DENO0[5] DENO0[4] DENO0[3] DENO0[2] DENO0[1] DENO0[0]
0
Reserved
0
0
Reserved
0
0
MDIV1[2]
0
0
MDIV1[1]
0
0
MDIV1[0]
0
0
0
VCO2_RA VCO2_RA
NGE1[1] NGE1[0]
0
0
0
Reserved
0
PLL2_1
MDIV2Setting
fVCO2 Range
NINT1[5] NINT1[4] NINT1[3] NINT1[2] NINT1[1] NINT1[0] NUME1[8] NUME1[7]
0
0
0
0
0
0
0
0
NUME1[6]
0
NUME1[5]
0
NUME1[4]
0
NUME1[3]
0
NUME1[2]
0
NUME1[1]
0
NUME1[0]
0
DENO1[8]
0
PLL2_1
NDIV2 Setting
38h
DENO1[7] DENO1[6] DENO1[5] DENO1[4] DENO1[3] DENO1[2] DENO1[1] DENO1[0]
0
0
0
0
0
0
0
0
draft-E-06
- 37 -
Sep -12