AK8140A Datasheet, PDF (35/45 Pages) Asahi Kasei Microsystems – Programmable Clock Generator

AK8140A
●Address：26h/2C MDIV1 Setting
Address
26h
2Bh
D7
MDIVCn[3]
D6
MDIVCn[2]
D5
MDIVCn[1]
Data
D4
D3
MDIVCn[0] MDIVPn[3]
D2
MDIVPn[2]
D1
MDIVPn[1]
*n=0/1
D0
MDIVPn[0]
MDIV1 Dividing Value Settings（MDIVCn， MDIVPn）
MDIV1Configuration is as the following Figure.
MDIV1 Dividing Value can be set according to Frequency Setting Procedure on page 10.
PLL1
Input CLK
MDIV1
MDIVCn[2]
1/2
1/3 or 1/4
1/2
MDIVCn[3:0]
Programmable
Div.
MDIVPn[3:0]
MDIVCn[1:0]
Phase
Comparator
Figure MDIV1Configuration
MDIVCn[3] ： Programmable divider input selection
*n=0/1
MDIVCn[3]
Input of Programmable divide
0
PLL1 Input CLK
1
PLL1 Input CLK 1/2
MDIVCn[2] ： 3or4 divider selection
MDIVCn[2]
0
1
Selected divider
3 divider
4 divider
*n=0/1
MDIVCn[1:0] ： Input of Phase comparator selection
*n=0/1
MDIVCn[1:0]
Input of Phase comparator
00
PLL1 Input CLK
01
PLL1 Input CLK 1/2
10
3 or4 divider output
11
Programmable divider Output
※Set MDIVCn[1:0]=‘11’, when INPUT_CK1 is set to‘1’(Address=21h)
draft-E-06
- 35 -
Sep -12