AK4691 Datasheet, PDF (66/80 Pages) Asahi Kasei Microsystems – 4ch ADC + 2ch DAC with MIC/HP/SPK-AMP

[AK4691]
Addr
01H
Register Name
Power Management 2
R/W
Default
D7
D6
D5
D4
D3
D2
D1
D0
0
HPMTN PMHPR PMHPL PMSPK PMLO PMDAC PMBP
RD
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
PMBP: BEEP Input Power Management
0: Power-down (default)
1: Power-up
Both PMDAC and PMBP bits should be set to “1” when DAC is powered-up for playback. After that, BEEPL,
BEEPH, BEEPS, MICL1, MICR1, or MICL2 bit is used to control each path when BEEP input is used.
PMDAC: DAC Power Management
0: Power-down (default)
1: Power-up
PMLO: Stereo Lineout Power Management
0: Power-down (default)
1: Power-up
PMSPK: Speaker-Amp Power Management
0: Power-down (default)
1: Power-up
PMHPL: Headphone-Amp Lch Power Management
0: Power-down (default)
1: Power-up
PMHPR: Headphone-Amp Rch Power Management
0: Power-down (default)
1: Power-up
HPMTN: Headphone-Amp Mute Control
0: Mute (default)
1: Normal operation
Each block can be powered-down respectively by writing “0” to each bit of this address. When the PDN pin is “L”, all
blocks are powered-down regardless as setting of this address. In this case, register is initialized to the default value.
When all power management bits are “0” in the 00H and 01H addresses, PMPLL bit and MCKO bit is “0”, all blocks
are powered-down. The register values remain unchanged.
When neither ADC nor DAC are used, external clocks may not be present. When ADC or DAC is used, external clocks
must always be present.
MS0672-E-00
- 66 -
2007/11