AK4691 Datasheet, PDF (59/80 Pages) Asahi Kasei Microsystems – 4ch ADC + 2ch DAC with MIC/HP/SPK-AMP

[AK4691]
■ Serial Control Interface
(1) 3-wire Serial Control Mode (I2CN pin = “H”)
(1)-1. Specific address WRITE Mode
Internal registers may be written by using the 3-wire µP interface pins (CSN, CCLK and CDTI). The data on this interface
consists of a 1-bit Chip address (Fixed to “1”), Read/Write (Fixed to “1”), Register address (MSB first, 6bits) and Control
data (MSB first, 8bits). Each bit is clocked in on the rising edge (“↑”) of CCLK. Writing data becomes effective between
the 16th CCLK rising edge (“↑”) and CSN rising edge (“↑”) after CSN falling edge(“↓”). CSN should be set to “H” every
one command. Clock speed of CCLK is 5MHz (max). The value of internal registers are initialized by the PDN pin = “L”.
CSN
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CCLK _{Clock, “H” or “L”}
Clock, “H” or “L”
CDTI “H” or “L”
C1 A5 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 “H” or “L”
“1”
“1”
C1:
R/W:
A5-A0:
D7-D0:
Chip Address; Fixed to “1”
READ/WRITE (“1”: WRITE, “0”: READ); Fixed to “1”
Register Address
Control data
Figure 40. Serial Control I/F Timing 1
MS0672-E-00
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2007/11