AK4691 Datasheet, PDF (15/80 Pages) Asahi Kasei Microsystems – 4ch ADC + 2ch DAC with MIC/HP/SPK-AMP

[AK4691]
Parameter
Symbol
PLL Slave Mode (PLL Reference Clock = MCKI pin)
MCKI Input Timing
Frequency
fCLK
Pulse Width Low
tCLKL
Pulse Width High
tCLKH
MCKO Output Timing
Frequency
fMCK
Duty Cycle
Except 256fs at fs=32kHz, 29.4kHz
dMCK
256fs at fs=32kHz, 29.4kHz
dMCK
LRCK Input Timing
Frequency
fs
Duty Cycle (Except TDM mode)
Duty
“H” time in TDM mode
tLRCKH
BICK Input Timing
Period
tBCK
Pulse Width Low
tBCKL
Pulse Width High
tBCKH
PLL Slave Mode (PLL Reference Clock = LRCK pin)
LRCK Input Timing
Frequency
fs
Duty Cycle (Except TDM mode)
Duty
“H” time in TDM mode
tLRCKH
BICK Input Timing
Period
tBCK
Pulse Width Low
tBCKL
Pulse Width High
tBCKH
PLL Slave Mode (PLL Reference Clock = BICK pin)
LRCK Input Timing
Frequency
fs
Duty Cycle (Except TDM mode)
Duty
“H” time in TDM mode
tLRCKH
BICK Input Timing
Period
PLL3-0 bits = “0010”
tBCK
PLL3-0 bits = “0011”
tBCK
Pulse Width Low
tBCKL
Pulse Width High
tBCKH
External Slave Mode
MCKI Input Timing
Frequency MCKI = 256fs
fCLK
MCKI = 512fs
fCLK
MCKI = 1024fs
fCLK
Pulse Width Low
tCLKL
Pulse Width High
tCLKH
LRCK Input Timing
Frequency MCKI = 256fs
fs
MCKI = 512fs
fs
MCKI = 1024fs
fs
Duty Cycle (Except TDM mode)
Duty
“H” time in TDM mode
tLRCKH
BICK Input Timing
Period
tBCK
Pulse Width Low
tBCKL
Pulse Width High
tBCKH
min
11.2896
0.4/fCLK
0.4/fCLK
0.2352
40
-
7.35
45
1/(16fs)
1/(64fs)
0.4 x tBCK
0.4 x tBCK
7.35
45
1/(16fs)
1/(64fs)
240
240
7.35
45
1/(16fs)
-
-
0.4 x tBCK
0.4 x tBCK
1.8816
3.7632
7.5264
0.4/fCLK
0.4/fCLK
7.35
7.35
7.35
45
1/(16fs)
312.5
130
130
typ
-
-
-
-
50
33
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1/(32fs)
1/(64fs)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
max
Units
27
-
-
12.288
60
-
48
55
1/(32fs)
1/(32fs)
-
-
MHz
ns
ns
MHz
%
%
kHz
%
ns
ns
ns
ns
48
kHz
55
%
1/(32fs)
ns
1/(32fs)
ns
-
ns
-
ns
48
kHz
55
%
1/(32fs)
ns
-
ns
-
ns
-
ns
-
ns
12.288
24.576
13.312
-
-
48
48
13
55
1/(32fs)
-
-
-
MHz
MHz
MHz
ns
ns
kHz
kHz
kHz
%
ns
ns
ns
ns
MS0672-E-00
- 15 -
2007/11