AK4691 Datasheet, PDF (53/80 Pages) Asahi Kasei Microsystems – 4ch ADC + 2ch DAC with MIC/HP/SPK-AMP

[AK4691]
LVDD
Rising Time (Note 53)
typ.
max
Falling Time (Note 54)
typ.
max.
3.6V
200ms
300ms
200ms
300ms
5.5V
220ms
400ms
260ms
440ms
Note 53. Rising time of stereo line output (0.9 x LVCM)
Note 54. Falling time of stereo line output (This time is until the voltage between 220Ω and 20kΩ resistors as shown in
Figure 34 becomes less than 50mV.)
Table 46. Rising / Falling time of stereo line output
[Stereo Line Output Control Sequence (in case of using Pop Reduction Circuit)]
E.g. In case of LVDD = 3.6V
(2)
P M L O b it
(1 )
(3)
L O P S bit
(5)
(4)
(6)
L O U T , R O U T p in s
N orm al O utput
≥ 300 m s
≥ 300 m s
Figure 35. Stereo Line Output Control Sequence (in case of using Pop Reduction Circuit)
(1) Set LOPS bit = “1”. Stereo line output enters the power-save mode.
(2) Set PMLO bit = “1”. Stereo line output exits the power-down mode.
LOUT and ROUT pins rise up to LVCM voltage. Rise time is 200ms (max 300ms) at C=1μF.
(3) Set LOPS bit = “0” after LOUT and ROUT pins rise up. Stereo line output exits the power-save mode.
Stereo line output is enabled.
(4) Set LOPS bit = “1”. Stereo line output enters power-save mode.
(5) Set PMLO bit = “1”. Stereo line output enters power-down mode.
LOUT and ROUT pins fall down to VSS4. Fall time is 200ms (max 300ms) at C=1μF.
(6) Set LOPS bit = “0” after LOUT and ROUT pins fall down. Stereo line output exits the power-save mode.
MS0672-E-00
- 53 -
2007/11