AK4691 Datasheet, PDF (55/80 Pages) Asahi Kasei Microsystems – 4ch ADC + 2ch DAC with MIC/HP/SPK-AMP

[AK4691]
■ Headphone Output
Power supply voltage for the Headphone-Amp is supplied from the LVDD pin and centered on the LVDD/2 voltage. The
load resistance is 16Ω (min). HPG bit selects the output voltage (Table 48).
HPG bit
0
1
Output Voltage [Vpp]
0.6 x AVDD
0.91 x AVDD
Table 48. Headphone-Amp Output Voltage
When the HPMTN bit is “0”, the common voltage of Headphone-Amp falls and the outputs (HPL and HPR pins) become
to “L” (VSS4). When HPMTN bit is “1”, the common voltage rises to LVDD/2. A capacitor between the MUTET pin and
ground reduces pop noise at power-up. Rise/Fall time constant is in proportional to LVDD voltage and the capacitor at the
MUTET pin.
LVDD
Capacitor value of
MUTET pin
HPMTN bit= “0” Æ “1”
(Note 55)
typ.
max
HPMTN bit = “1” Æ “0”
(Note 56)
typ.
max.
3.6V
1μF±30%
120ms
210ms
140ms
260ms
5.5V
160ms
270ms
170ms
300ms
3.6V
5.5V
2.2μF±30%
260ms
340ms
460ms
590ms
310ms
370ms
560ms
600ms
Note 55. Rising time of HP-Amp (0.8 x LVDD/2)
Note 56. Time until the common voltage settles to VSS4
Table 49. Relationship between capacitor value of MUTET pin and MUTE ON/OFF time (HPG bit = “0”)
When PMHPL and PMHPR bits are “0”, the Headphone-Amp is powered-down, and the outputs (HPL and HPR pins)
become to “L” (VSS4).
PMHPL/R bits
0
1
HPMTN bit
Mode
HPL pin
HPR pin
x
Power-down
“L”(VSS4)
“L”(VSS4)
0
Fall down to
common voltage
“L”(VSS4)
“L”(VSS4)
1
Rise up to common
voltage
Normal operation Normal operation
Table 50. Headphone-Amp Mode Setting (x: Don’t care)
(default)
MS0672-E-00
- 55 -
2007/11