AK4691 Datasheet, PDF (43/80 Pages) Asahi Kasei Microsystems – 4ch ADC + 2ch DAC with MIC/HP/SPK-AMP

[AK4691]
3. Example of ALC Operation
Table 33 shows the examples of the ALC setting for MIC recording.
Register Name
LMTH1-0
ZELMN
ZTM1-0
WTM2-0
REF7-0
IVL7-0,
IVR7-0
LMAT1-0
RGAIN1-0
ALC
Comment
fs=8kHz
Data
Operation
Limiter detection Level
01
−4.1dBFS
Limiter zero crossing detection
0
Enable
Zero crossing timeout period
01
32ms
Recovery waiting period
*WTM2-0 bits should be the same or 001
32ms
larger data to ZTM1-0 bits
Maximum gain at recovery operation E1H
+30dB
Gain of IVOL
E1H
+30dB
Limiter ATT step
00
1 step
Recovery GAIN step
00
1 step
ALC enable
1
Enable
Table 33. Example of the ALC setting
fs=48kHz
Data
Operation
01
−4.1dBFS
0
Enable
11
21.3ms
011
21.3ms
E1H
+30dB
E1H
+30dB
00
1 step
00
1 step
1
Enable
The following registers should not be changed during the ALC operation. These bits should be changed after the ALC
operation is finished by ALC bit = “0” or PMADC1=PMADC2 = PMDAC bits = “0”.
• LMTH1-0, LMAT1-0, WTM2-0, ZTM1-0, RGAIN1-0, REF7-0, ZELMN, GSEL, RFST1-0, LFST bits
Manual Mode
Example:
MIC Input Recording
Limiter = Zero crossing Enable
Recovery Cycle = 21.3ms@48kHz
Zero Crossing Timeout Period = 21.3ms@48kHz
Limiter and Recovery Step = 1
Fast Limiter/Recovery Speed = 4 step
Gain of IVOL = +30.0dB
Maximum Gain = +30.0dB
Limiter Detection Level = −4.1dBFS
LFST bit = “0”
ALC bit = “1”
WR (ZTM1-0, WTM2-0)
(1) Addr=0AH, Data=1BH
WR (ZELMN, RGAIN1-0, LMAT1-0)
(2) Addr=0BH, Data=00H
WR (LFST, RFST1-0, GSEL, LMTH1-0)
(3) Addr=0CH, Data=01H
WR (REF7-0)
* The value of IVL/R should be
the same or smaller than REF’s
(4) Addr=0DH, Data=E1H
WR (IVL/R7-0)
(5) Addr=0EH & 10H, Data=E1H
WR (ALC= “1”)
(6) Addr=12H, Data=04H
ALC Operation
Note : WR : Write
Figure 26. Registers set-up sequence at ALC operation
MS0672-E-00
- 43 -
2007/11