AK4691 Datasheet, PDF (28/80 Pages) Asahi Kasei Microsystems – 4ch ADC + 2ch DAC with MIC/HP/SPK-AMP

[AK4691]
64BICK
LRCK
01 23
BICK(64fs)
SDTO1(o) 15 14 13
L1
SDTO2(o)
15 16 17 18
31 0 1 2 3
15 16 17 18
31 0 1
1 0 15 14
R1
1 0 15 14 13
1 0 15 14
1 0 15
L2
16 BICK
"L" Output
R2
16 BICK
SDTI(i)
15 14 13
1 0 15 14
10
Don't Care
15
15:MSB, 0:LSB
Lch Data
Rch Data
16 BICK
16 BICK
Note 48. When PMADC1 bit is “0”, SDTO1 is output to “0” data during the period of L1 and R1. When PMADC2 bit is
“0”, SDTO2 is output to “0” data during the period of L2 and R2.
Figure 17. Mode 0 Timing (TDM Mode)
LRCK
0123
BICK(32fs)
SDTO(o)
15 14 13
9 10 11 12 13 14 15 0 1 2 3
7 6 5 4 3 2 1 0 15 14 13
9 10 11 12 13 14 15 0 1
7 6 5 4 3 2 1 0 15
SDTI(i)
15 14 13
0123
BICK(64fs)
SDTO(o)
15 14 13
7 6 5 4 3 2 1 0 15 14 13
15 16 17 18
31 0 1 2 3
10
15 14 13
7 6 5 4 3 2 1 0 15
15 16 17 18
31 0 1
10
15
SDTI(i)
Don't Care
15:MSB, 0:LSB
15 14
10
Don't Care
15 14
Lch Data
Rch Data
Figure 18. Mode 1 Timing
210
MS0672-E-00
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2007/11