AK4691 Datasheet, PDF (62/80 Pages) Asahi Kasei Microsystems – 4ch ADC + 2ch DAC with MIC/HP/SPK-AMP

[AK4691]
(2)-2. READ Operations
Set the R/W bit = “1” for the READ operation of the AK4691. After transmission of data, the master can read the next
address’s data by generating an acknowledge instead of terminating the write cycle after receiving the first data word.
After receiving each data packet the internal 5-bit address counter is incremented, and the next data is automatically taken
into the next address. If the address exceeds 33H prior to generating a stop condition, the address counter will “roll over”
to 00H and the previous data will be overwritten.
The AK4691 supports two basic read operations: CURRENT ADDRESS READ and RANDOM ADDRESS READ.
(2)-2-1. CURRENT ADDRESS READ
The AK4691 contains an internal address counter. The “current address read” operation reads the data appointed by the
counter. The counter is incremented by one from the address number of the last word accessed. Therefore, if the last
access (either a read or write) were to address n, the next CURRENT READ operation would access data from the address
n+1. After receiving the slave address with R/W bit “1”, the AK4691 generates an acknowledge, transmits 1-byte of data
to the address set by the internal address counter and increments the internal address counter by 1. If the master does not
generate an acknowledge but instead generates a stop condition, the AK4691 ceases transmission.
S
T
A
R/W="1"
R
T
SDA
Slave
S _Address
A
C
K
Data(n)
Data(n+1)
Data(n+2)
MA
MA
MA
AC
AC
AC
S
T
K
S
T
K
S
T
K
E
E
E
R
R
R
Figure 46. CURRENT ADDRESS READ
S
T
O
P
Data(n+x)
P
MA
MN
AC
AA
S
T
K
E
S
T
E
C
K
R
R
(2)-2-2. RANDOM ADDRESS READ
The random read operation allows the master to access any memory location at random. Prior to issuing the slave address
with the R/W bit set to “1”, the master must first perform a “dummy” write operation. The master issues a start request, a
slave address (R/W bit = “0”) and then the register address to read. After the register address is acknowledged, the master
immediately reissues the start request and the slave address with the R/W bit “1”. The AK4691 then generates an
acknowledge, 1 byte of data and increments the internal address counter by 1. If the master does not generate an
acknowledge but instead generates a stop condition, the AK4691 ceases transmission.
S
T
A
R/W ="0"
R
T
S
T
A
R/W ="1"
R
T
SDA
Slave
S _Address
Sub
Address(n)
Slave
S _Address
Data(n)
Data(n+1)
A
A
A
MA
MA
C
K
C
K
C
K
AC
S
T
K
A
S
T
C
K
E
E
R
R
Figure 47. RANDOM ADDRESS READ
S
T
O
P
Data(n+x)
P
MA
MN
A
S
T
C
K
A
S
T
A
C
E
EK
R
R
MS0672-E-00
- 62 -
2007/11