AK4691 Datasheet, PDF (25/80 Pages) Asahi Kasei Microsystems – 4ch ADC + 2ch DAC with MIC/HP/SPK-AMP

[AK4691]
■ PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
A reference clock of PLL is selected among the input clocks to the MCKI, BICK or LRCK pin. The required clock to the
AK4691 is generated by an internal PLL circuit. Input frequency is selected by PLL3-0 bits (Table 4).
a) PLL reference clock: MCKI pin
The BICK and LRCK inputs should be synchronized with the MCKO output. The phase between MCKO and LRCK dose
not matter. The MCKO pin outputs the frequency selected by PS1-0 bits (Table 9) and the output is enabled by MCKO
bit. Sampling frequency can be selected by FS3-0 bits (Table 5).
AK4691
11.2896MHz, 12MHz, 12.288MHz
13.5MHz, 24MHz, 27MHz
DSP or μP
MCKI
MCKO
BICK
LRCK
256fs/128fs/64fs/32fs
≥ 32fs
1fs
MCLK
BCLK
LRCK
SDTO1/2
SDTI
SDTI1/2
SDTO
Figure 14. PLL Slave Mode 1 (PLL Reference Clock: MCKI pin)
b) PLL reference clock: BICK or LRCK pin
Sampling frequency corresponds to 7.35kHz to 48kHz by changing FS3-0 bits (Table 6).
AK4691
MCKO
MCKI
BICK
LRCK
SDTO1/2
SDTI
DSP or μP
32fs, 64fs
1fs
BCLK
LRCK
SDTI1/2
SDTO
Figure 15. PLL Slave Mode 2 (PLL Reference Clock: LRCK or BICK pin)
The external clocks (MCKI, BICK and LRCK) should always be present whenever the ADC or DAC is in operation
(PMADC1 bit = “1”, PMADC2 bit = “1” or PMDAC bit = “1”). If these clocks are not provided, the AK4691 may draw
excess current and it is not possible to operate properly because utilizes dynamic refreshed logic internally. If the external
clocks are not present, the ADC and DAC should be in the power-down mode (PMADC1=PMADC2=PMDAC bits =
“0”).
MS0672-E-00
- 25 -
2007/11