AK4691 Datasheet, PDF (54/80 Pages) Asahi Kasei Microsystems – 4ch ADC + 2ch DAC with MIC/HP/SPK-AMP

[AK4691]
2. LMODE bit = “0” (When Line input and Line output are used as a common connector.)
When PMLO bit bit = “0”, the stereo line output enters power-down mode and the output becomes Hi-Z status. When the
LOPS bit is “1”, stereo line output (LOUT/ROUT pins) enters power-save mode and outputs LVCM voltage via an
internal resistor (typ. 200kΩ). In power-save mode, the signal path of stereo line output (DACL, BEEPL, MICL1,
MICL2, and MICR1 bits) is OFF. Pop noise can be decreased by using power-save mode. When using line input, the
AK4691 should be in the power-save mode.
PMLO bit LOPS bit
Mode
LOUT/ROUT pins
0
x
Power-down
Hi-Z
(default)
1
1
Power-save
LVCM
0
Normal Operation
Normal Operation
Table 47. External Circuit for Stereo Line Output @ LMODE bit = “0” (x: Don’t care)
Connector
LIN pin
6.2kΩ ^{(RIN pin)}
6.2kΩ
LOUT pin
(ROUT pin)
typ.60kΩ /100kΩ
typ.100kΩ
AIN bit = “1”
-
+
MIX-Amp
From Pre-Amp1
typ. 60kΩ
VCOM
PRE bit = “0”
typ.200kΩ
LVCM
To ADC1
Power-save Mode
Figure 36. Connection Example (When Line input and Line output are used as a common connector.)
MS0672-E-00
- 54 -
2007/11