AK4691 Datasheet, PDF (23/80 Pages) Asahi Kasei Microsystems – 4ch ADC + 2ch DAC with MIC/HP/SPK-AMP

[AK4691]
■ PLL Unlock State
1) PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
In this mode, the LRCK and BICK pins change to “L” and irregular frequency clock is output from the MCKO pin at
MCKO bit is “1” before the PLL sets to lock state after PMPLL bit = “0” Æ “1”. If MCKO bit is “0”, the MCKO pin
changes to “L” (Table 7).
After the PLL is locked, a first period of LRCK and BICK may be invalid clock, but these clocks return to normal state
after a period of 1/fs.
When sampling frequency is changed, the BICK and LRCK pins do not output irregular frequency clocks but change to
“L” by setting PMPLL bit to “0”.
PLL State
After after PMPLL bit “0” Æ “1”
MCKO pin
MCKO bit = “0” MCKO bit = “1”
“L” Output
Invalid
BICK pin
“L” Output
PLL Unlock (except above case)
“L” Output
Invalid
Invalid
PLL Lock
“L” Output
Table 9
Table 10
Table 7. Clock Operation at PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
LRCK pin
“L” Output
Invalid
1fs Output
2) PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
In this mode, an invalid clock is output from the MCKO pin before the PLL sets to lock state after PMPLL bit = “0” Æ
“1”. Then, the clock selected by Table 9 is output from the MCKO pin when PLL is locked. ADC and DAC output invalid
data when the PLL is unlocked. For DAC, the output signal can be muted by writing “0” to DACL, DACH and DACS
bits.
PLL State
After that PMPLL bit “0” Æ “1”
MCKO pin
MCKO bit = “0” MCKO bit = “1”
“L” Output
Invalid
PLL Unlock
“L” Output
Invalid
PLL Lock
“L” Output
Output
Table 8. Clock Operation at PLL Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
MS0672-E-00
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2007/11