AK4691 Datasheet, PDF (26/80 Pages) Asahi Kasei Microsystems – 4ch ADC + 2ch DAC with MIC/HP/SPK-AMP

[AK4691]
■ EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
When PMPLL bit is “0”, the AK4691 becomes EXT mode. Master clock is input directly from MCKI pin without the
internal PLL circuit. This mode is compatible with I/F of the normal audio CODEC. The clocks required to operate are
MCKI (256fs, 512fs or 1024fs), LRCK (fs) and BICK (≥32fs). The master clock (MCKI) should be synchronized with
LRCK. The phase between these clocks does not matter. The input frequency of MCKI is selected by FS1-0 bits (Table
11).
Mode
FS3-2 bits
FS1 bit FS0 bit
MCKI Input
Frequency
Sampling Frequency
Range
0
x
0
0
256fs
7.35kHz ∼ 48kHz (default)
1
x
0
1
1024fs
7.35kHz ∼ 13kHz
2
x
1
0
512fs
7.35kHz ∼ 48kHz
3
x
1
1
512fs
7.35kHz ∼ 26kHz
Others
Others
N/A
N/A
Table 11. MCKI Frequency at EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”), (N/A: Not available, x: Don’t care)
The S/N of the DAC at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise.
The out-of-band noise can be reduced by using higher frequency of the master clock. The S/N of the DAC output through
the LOUT/ROUT pins at fs=8kHz is shown in Table 12.
Mode
MCKI
S/N
(fs=8kHz, 20kHzLPF + A-weighted)
0
256fs
2
512fs
80dB
3
512fs
90dB
1
1024fs
90dB
Table 12. Relationship between MCKI and S/N of LOUT/ROUT pins
The external clocks (MCKI, BICK and LRCK) should always be present whenever the ADC or DAC is in operation
(PMADC1 bit = “1”, PMADC2 bit = “1” or PMDAC bit = “1”). If these clocks are not provided, the AK4691 may draw
excess current and it is not possible to operate properly because utilizes dynamic refreshed logic internally. If the external
clocks are not present, the ADC and DAC should be in the power-down mode (PMADC1=PMADC2=PMDAC bits =
“0”).
AK4691
MCKO
MCKI
BICK
LRCK
256fs, 512fs or 1024fs
DSP or μP
MCLK
≥ 32fs
BCLK
1fs
LRCK
SDTO1/2
SDTI
SDTI1/2
SDTO
Figure 16. EXT Slave Mode
MS0672-E-00
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2007/11