AK4691 Datasheet, PDF (39/80 Pages) Asahi Kasei Microsystems – 4ch ADC + 2ch DAC with MIC/HP/SPK-AMP

[AK4691]
■ ALC Operation
The ALC (Automatic Level Control) is operated by ALC block when ALC bit is “1”. The ALC block is common to
ADC1 and ADC2. When only DAC is powered-up, ALC circuit operates at playback path. When only ADC1 or ADC2 is
powered-up or ADC1, ADC2, and DAC are powered-up, ALC circuit operates at recording path.
PMADC2 -1 bits
PMDAC bit
LOOP1-0 bits
(Note 52)
Status
ALC
00
0
x
1
x
Power-down
Playback
Power-down
Playback path
01, 10 or 11
0
1
x
Recording
Recording path
00
Recording & Playback
Recording path
01
1
01, 11
Recording Monitor Playback
(ADC1 Æ DAC)
Recording path
10
Recording & Playback
Recording path
01
Recording & Playback
Recording path
10
1
10, 11
Recording Monitor Playback Recording path
(ADC2 Æ DAC)
Recording path
Recording (ADC2)
01, 11
Recording Monitor Playback Recording path
11
1
(ADC1 Æ DAC)
Recording (ADC1)
10
Recording Monitor Playback Recording path
(ADC2 Æ DAC)
Note 52. When LOOP1-0 bits = “10”, TDM mode (DIF1-0 bits = “00”) is not supported.
Table 25. ALC Setting (x: Don’t care)
(default)
1. ALC Limiter Operation
During the ALC limiter operation, when either Lch or Rch in ADC1 and ADC2 exceeds the ALC limiter detection level
(Table 26), the IVL and IVR values (same value) are attenuated automatically by the amount defined by the ALC limiter
ATT step (Table 27). The IVL and IVR are then set to the same value for both channels.
When ZELMN bit = “0” (zero cross detection is enabled), the IVL and IVR values are changed by ALC limiter operation
at the individual zero crossing points of Lch and Rch or at the zero crossing timeout. ZTM1-0 bits set the zero crossing
timeout period of both ALC limiter and recovery operation (Table 28). When ALC output level exceeds full-scale at
LFST bit = “1”, IVL and IVR values are immediately (Period: 1/fs) changed. When ALC output level is less than
full-scale, IVL and IVR values are changed at the individual zero crossing point of each channels or at the zero crossing
timeout. When LFST bit = “1”, the attenuation level is fixed to 1 step regardless of the setting of LMAT1-0 bits.
When ZELMN bit = “1” (zero cross detection is disabled), IVL and IVR values are immediately (period: 1/fs) changed by
ALC limiter operation. Attenuation step is fixed to 1 step regardless of the setting of LMAT1-0 bits.
The attenuate operation is executed continuously until the input signal level becomes ALC limiter detection level (Table
26) or less. After completing the attenuate operation, unless ALC bit is changed to “0”, the operation repeats when the
input signal level exceeds LMTH1-0 bits.
The ALC operation corresponds to the impulse noise. When the impulse noise is input at ZELNN bit = “0”, the ALC
limiter operation becomes faster than the setting of ZTM1-0 bits (fast limiter operation). The speed of fast limiter
operation is set by RFST1-0 bits (Table 32).
MS0672-E-00
- 39 -
2007/11