AK4691 Datasheet, PDF (17/80 Pages) Asahi Kasei Microsystems – 4ch ADC + 2ch DAC with MIC/HP/SPK-AMP

■ Timing Diagram
MCKI
BICK
LRCK
MCKO
1/fCLK
tCLKH
tCLKL
tBCK
VIH1
VIL1
tBCKH
tBCKL
1/fs
50%TVDD1
dBCK = tBCKH / tBCK x 100
tBCKL / tBCK x 100
tLRCKH
tLRCKL
1/fMCK
50%TVDD1
Duty = tLRCKH x fs x 100
tLRCKL x fs x 100
50%TVDD1
tMCKL
dMCK = tMCKL x fMCK x 100
Figure 3. Clock Timing (PLL Master mode)
[AK4691]
LRCK
BICK
SDTO
SDTI
50%TVDD1
tMBLR
tLRD
tBSD
50%TVDD1
50%TVDD1
tSDS
tSDH
VIH1
VIL1
Figure 4. Audio Interface Timing (PLL Master mode)
MS0672-E-00
- 17 -
2007/11