AK4691 Datasheet, PDF (44/80 Pages) Asahi Kasei Microsystems – 4ch ADC + 2ch DAC with MIC/HP/SPK-AMP

[AK4691]
■ FADEIN Mode
In FADEIN Mode, the IVL/R values increase gradually by the step set by FDATT1-0 bits when FDIN bit changes from
“0” to “1”. The FADEIN period is set by REF7-0, FDATT1-0 (Table 35) and FDTM1-0 (Table 34) bits. The FADEIN
operation is executed by the zero crossing detection. The operation stops when the IVL/R values become the REF value or
the limiter detection level (LMTH1-0). If the limiter operation is executed during FADAIN period, the FADEIN
operation stops and the ALC operation starts.
NOTE: When FDIN and FDOUT bits are set to “1” at the same time, FADEOUT operation is prior to FADEIN operation.
SDTO1, 2
IVL/R7-0 bits XXH
00H
ALC bit
FDIN bit
(5)
(1) (2)
(3)
(4)
Figure 27. Example for controlling sequence in FADEIN operation
(1) WR(IVL/R7-0 bits = 00H) : IVL/R are changed to “MUTE”.
(2) WR (ALC bit = FDIN bit = “0”): The ALC operation is disabled. To start the FADEIN operation, FDIN bit is written
in “0”.
(3) WR (ALC bit = FDIN bit = “1”): The FADEIN operation starts. The IVL/R is fade-in from MUTE state.
(4) The FADEIN operation is repeated until the limiter detection level (LMTH1-0 bits) or the reference level (REF7-0
bits). After completing the FADEIN operation, the ALC operation starts.
(5) FADEIN time is set by REF7-0, FDTM1-0, and FDATT bits
e.g. REF7-0 = E1H(225 dec), FDTM1-0 = “01” (= 42.7ms @ fs = 48kHz), FDATT1-0 = 2 step
(225 x FDTM1-0) / FDATT1-0 = 225 x 42.7ms /2 = 4.8s
FDTM1 bit
0
0
1
1
FDTM0 bit
0
1
0
1
FADEIN/OUT Period
8kHz
32kHz
48kHz
1024/fs
128ms
32ms
21.3ms
2048/fs
256ms
64ms
42.7ms
2304/fs
288ms
72ms
48ms
2560/fs
320ms
80ms
53.3ms
Table 34. FADEIN/OUT Period
FDATT1 bit FDATT0 bit ATT STEP
0
0
1
0
1
2
1
0
3
1
1
4
Table 35. FADEIN/OUT ATT Step Setting
(default)
(default)
MS0672-E-00
- 44 -
2007/11