AK4691 Datasheet, PDF (40/80 Pages) Asahi Kasei Microsystems – 4ch ADC + 2ch DAC with MIC/HP/SPK-AMP

[AK4691]
LMTH1
bit
0
0
1
1
LMTH0
bit
ALC Limiter Detection Level
ALC Recovery Waiting Counter Reset Level
0
ALC Output ≥ −2.5dBFS
−2.5dBFS > ALC Output ≥ −4.1dBFS
1
ALC Output ≥ −4.1dBFS
−4.1dBFS > ALC Output ≥ −6.0dBFS
0
ALC Output ≥ −6.0dBFS
−6.0dBFS > ALC Output ≥ −8.5dBFS
1
ALC Output ≥ −8.5dBFS
−8.5dBFS > ALC Output ≥ −12dBFS
Table 26. ALC Limiter Detection Level / Recovery Counter Reset Level
(default)
ZELMN
bit
0
1
LMAT1
bit
0
0
1
1
x
ALC Limiter ATT Step
LMAT0 _ALC
ALC
ALC
ALC
bit _{Output ≥ Output ≥ Output ≥ Output ≥}
LMTH
FS
FS + 6dB FS + 12dB
1step
1step
1step
1step
0
(default)
(0.375dB) (0.375dB) (0.375dB) (0.375dB)
2 step
2 step
2 step
2 step
1
(0.75dB) (0.75dB) (0.75dB) (0.75dB)
2 step
4 step
4 step
8 step
0
(0.75dB) (1.5dB) (1.5dB) (3.0dB)
1step
2 step
4 step
8 step
1
(0.375dB) (0.75dB) (1.5dB) (3.0dB)
1 step
1 step
1 step
1 step
x
(0.375dB) (0.375dB) (0.375dB) (0.375dB)
Table 27. ALC Limiter ATT Step (x: Don’t care)
ZTM1 bit
0
0
1
1
ZTM0 bit
0
1
0
1
Zero Crossing Timeout Period
8kHz
32kHz
48kHz
128/fs
16ms
4ms
2.7ms
256/fs
32ms
8ms
5.3ms
512/fs
64ms
16ms
10.7ms
1024/fs
128ms
32ms
21.3ms
Table 28. ALC Zero Crossing Timeout Period
(default)
MS0672-E-00
- 40 -
2007/11