AK4691 Datasheet, PDF (27/80 Pages) Asahi Kasei Microsystems – 4ch ADC + 2ch DAC with MIC/HP/SPK-AMP

[AK4691]
■ System Reset
When power-up, the AK4691 should be reset by bringing the PDN pin = “L”. This ensures that all internal registers reset
to their initial values.
The ADC enters an initialization cycle when the PMADC1 or PMADC2 bit is changed from “0” to “1” at PMDAC bit =
“0”. The initialization cycle time is 1059/fs=22ms@fs=48kHz. During the initialization cycle, the ADC digital data
outputs of both channels are forced to a 2's complement, “0”. The ADC output reflects the analog input signal after the
initialization cycle is complete.
The DAC enters an initialization cycle when the PMDAC bit is changed from “0” to “1” at PMADC1 = PMADC2 =
INITDA bits = “0”. The initialization cycle time is 1059/fs=22ms@fs=48kHz. During the initialization cycle, the DAC
input digital data of both channels are internally forced to a 2's complement, “0”. The DAC output reflects the digital input
data after the initialization cycle is complete and group delay of DAC (26/fs = 0.54ms @ fs=48kHz) is passed. When
INITDA bits = “1”, the DAC does not do initialization cycle. When PMADC1 or PMADC 2 bit is “1”, INITDA bit should
be set to “0”. When PMDAC bit is “0”, INITDA bit should be changed.
■ Audio Interface Format
Four types of data formats are available and are selected by setting the DIF1-0 bits (Table 13). In all modes, the serial data
is MSB first, 2’s complement format. Audio interface formats can be used in both master and slave modes. LRCK and
BICK are output from the AK4691 in master mode, but must be input to the AK4691 in slave mode. The SDTO is clocked
out on the falling edge (“↓”) of BICK and the SDTI is latched on the rising edge (“↑”). SDTO1’s Audio interface
format is the same as SDTO2’s.
Mode
0
1
2
3
DIF1 bit
0
0
1
1
DIF0 bit
0
1
0
1
SDTO1 (ADC1)
SDTO2 (ADC2)
SDTI (DAC)
TDM Mode
TDM Mode
MSB justified LSB justified
MSB justified
I²S compatible
MSB justified
I²S compatible
Table 13. Audio Interface Format
BICK
64fs
≥ 32fs
≥ 32fs
≥ 32fs
Figure
Figure 17
Figure 18
Figure 19
Figure 20
(default)
If 16-bit data that ADC outputs is converted to 8-bit data by removing LSB 8-bit, “−1” at 16bit data is converted to “−1”
at 8-bit data. And when the DAC playbacks this 8-bit data, “−1” at 8-bit data will be converted to “−256” at 16-bit data
which is a large offset. This offset can be removed by adding the offset of “128” to 16-bit data before converting to 8-bit
data.
MS0672-E-00
- 27 -
2007/11