AK4691 Datasheet, PDF (21/80 Pages) Asahi Kasei Microsystems – 4ch ADC + 2ch DAC with MIC/HP/SPK-AMP

[AK4691]
OPERATION OVERVIEW
■ System Clock
There are the following four clock modes to interface with external devices (Table 1, Table 2).
Mode
PMPLL bit
M/S bit
PLL3-0 bits
Figure
PLL Master Mode
1
1
Table 4
Figure 13
PLL Slave Mode 1
(PLL Reference Clock: MCKI pin)
1
0
Table 4
Figure 14
PLL Slave Mode 2
(PLL Reference Clock: LRCK or BICK pin)
1
0
Table 4
Figure 15
EXT Slave Mode
0
0
x
Figure 16
Don’t Care (Note 47)
0
1
x
-
Note 47. If this mode is selected, the invalid clocks are output from the MCKO pin when MCKO bit is “1”.
Table 1. Clock Mode Setting (x: Don’t care)
Mode
PLL Master Mode
PLL Slave Mode
(PLL Reference Clock: MCKI pin)
MCKO bit
0
1
0
1
MCKO pin
L
Selected by
PS1-0 bits
L
Selected by
PS1-0 bits
MCKI pin
Selected by
PLL3-0 bits
Selected by
PLL3-0 bits
PLL Slave Mode
(PLL Reference Clock: LRCK or BICK pin)
0
L
GND
EXT Slave Mode
0
L
Selected by
FS3-0 bits
Table 2. Clock pins state in Clock Mode
BICK pin
Output
(Selected by
BCKO bit)
Input
(≥ 32fs)
Output
(Selected by
BCKO bit)
Input
(≥ 32fs)
LRCK pin
Output
(1fs)
Input
(1fs)
Input
(1fs)
Input
(1fs)
■ Master Mode/Slave Mode
The M/S bit selects either master or slave mode. M/S bit = “1” selects master mode and “0” selects slave mode. When the
AK4691 is power-down mode (PDN pin = “L”) and exits reset state, the AK4691 is slave mode. After exiting reset state,
the AK4691 is set to master mode by changing M/S bit = “1”.
When the AK4691 is used by master mode, the LRCK and BICK pins are a floating state until M/S bit becomes “1”. The
LRCK and BICK pins of the AK4691 should be pulled-down or pulled-up by the resistor (about 100kΩ) externally to
avoid the floating state.
M/S bit
Mode
0
Slave Mode
1
Master Mode
Table 3. Select Master/Slave Mode
(default)
MS0672-E-00
- 21 -
2007/11