AK4691 Datasheet, PDF (60/80 Pages) Asahi Kasei Microsystems – 4ch ADC + 2ch DAC with MIC/HP/SPK-AMP

[AK4691]
(1)-2. Continuous Data WRITE Mode
In this mode, data can be written continuously and address counter is incremented automatically.
Internal registers may be written by the 3-wire µP interface pins (CSN, CCLK and CDTI). The data on this interface
consists of a 1-bit Chip address (Fixed to “1”), Read/Write (Fixed to “1”), Register address (MSB first, 6bits) and Control
data (MSB first, 8bits x N). Each bit is clocked in on the rising edge (“↑”) of CCLK. Writing data becomes effective
between the 16th CCLK rising edge (“↑”) and falling edge (“↓”). When the μP continues sending CDTI and CCLK in
CSN = “L”, address counter is incremented automatically, and writing data becomes effective between the 8^th CCLK
rising edge (“↑”) and falling edge (“↓”). For the last address (33H), writing data becomes effective between the 8^th CCLK
rising edge (“↑”) and CSN rising edge (“↑”).
When data is written to an arbitrary address before the last address, WRITE operation can be finished by setting CSN =
“H”.
Note 58. When CSN is set to “H” while data is written, the data is ignored.
Note 59. After data in the last address (33H) becomes effective, CSN should be set to “H”. If the uP continues sending
CCLK and CDTI in CSN = “L”, data is rewritten in address 33H.
CSN
CCLK
01 2 34 56 7 89
Clock, ‘H’ or ‘L’
14 15 0 1
67
CDTI ‘H’ or ‘L’
C1 A5 R/W A4 A3 A2 A1 A0 D7 D6
D1 D0 D7 D6
D1 D0
“1”
“1”
Data (n)
Data (n+1)
Address (n)
C1:
R/W:
A5-A0:
D7-D0:
Chip Address (C1= “1”); Fixed to “1”
READ/WRITE (“1”: WRITE, “0”: READ); Fixed to “1”
Register Address
Control data
01
67
Clock, ‘H’ or ‘L’
D7 D6
D1 D0 ‘H’ or ‘L’
Data (n+N-1)
Figure 41. Control Data Timing 2
MS0672-E-00
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2007/11