AK4691 Datasheet, PDF (47/80 Pages) Asahi Kasei Microsystems – 4ch ADC + 2ch DAC with MIC/HP/SPK-AMP

[AK4691]
When writing to the IVL7-0 and IVR7-0 bits continuously, the control register should be written in an interval more than
zero crossing timeout. If not, IVL and IVR are not changed since zero-crossing counter is reset at every write operation. If
the same register value as the previous write operation is written to IVL and IVR, this write operation is ignored and
zero-crossing counter is not reset. Therefore, IVL and IVR can be written in an interval less than zero crossing timeout.
ALC bit
ALC Status
Disable
Enable
Disable
IVL7-0 bits
E1H(+30dB)
IVR7-0 bits
C6H(+20dB)
Internal IVL
Internal IVR
E1H(+30dB)
C6H(+20dB)
E1(+30dB) --> F1(+36dB)
(1)
E1(+30dB) --> F1(+36dB)
E1(+30dB)
(2)
C6H(+20dB)
Figure 29. IVOL value during ALC operation (GSEL bit = “0”)
(1) The IVL value becomes the start value if the IVL and IVR are different when the ALC starts.
(2) Writing to IVL and IVR registers (0EH, 10H) is ignored during ALC operation. After ALC is disabled, the IVOL
changes to the last written data by zero crossing or timeout. When ALC is enabled again, ALC bit should be set to “1”
with an interval more than zero crossing timeout period after ALC bit = “0”.
■ De-emphasis Filter
The AK4691 includes the digital de-emphasis filter (tc = 50/15μs) by IIR filter. Setting the DEM1-0 bits enables the
de-emphasis filter (Table 37).
DEM1 bit DEM0 bit
Mode
0
0
44.1kHz
0
1
OFF
1
0
48kHz
1
1
32kHz
Table 37. De-emphasis Control
(default)
MS0672-E-00
- 47 -
2007/11