Z89323 Datasheet, PDF (57/61 Pages) Zilog, Inc. – 16-BIT DIGITAL SIGNAL PROCESSORS

CLOCK
/RESET
INTERNAL
RESET
EXECUTE
PRELIMINARY
TCY
RSET
RWIDTH
RRISE
Z89323/373/393
16-BIT DIGITAL SIGNAL PROCESSORS
Cycle 0
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5 Code Exec
RD//WR
/DS
UO0-1
EA0-2
EXT0-15
Tri-Stated
PA0-15
RAM/
REGISTERS
Tri-Stated
Access Reset Vector
Intact*
* The RAM and hardware registers are left intact
during a warm reset. A cold reset will produce
random data in these locations. The status
register is set to zeroes in both cases.
Figure 48. RESET Timing
CLOCK
TCY
PROGRAM
ADDRESS
PROGRAM
DATA
PAVALID
Valid
PDSET
Valid
Valid
PDHOLD
Valid
Valid
Valid
Figure 49. External Program Memory Port Timing
DS95DSP0101 Q4/95
57