Z89323 Datasheet, PDF (37/61 Pages) Zilog, Inc. – 16-BIT DIGITAL SIGNAL PROCESSORS

FUNCTIONAL DESCRIPTION
PRELIMINARY
Z89323/373/393
16-BIT DIGITAL SIGNAL PROCESSORS
Instruction Timing. Most instructions are executed in one
machine cycle. Long immediate instructions and Jump or
Call instructions are executed in two machine cycles. A
multiplication or multiplication/accumulate instruction
requires a single cycle. Specific instruction cycle times are
described in the Condition Code section.
Multiply/Accumulate. The multiplier can perform a 16-bit
x 16-bit multiply, or multiply accumulate, in one machine
cycle using the Accumulator and/or both the X and Y
inputs. The multiplier produces a 32-bit result, however,
only the 24 most significant bits are saved for the next
instruction or accumulation. For operations on very small
numbers where the least significant bits are important, the
data should first be scaled by eight bits (or the multiplier
and multiplicand by four bits each) to avoid truncation
errors. Note that all inputs to the multiplier should be
fractional two’s-complement, 16-bit binary numbers (Figure
29). This puts them in the range [–1 to 0.9999695], and the
result is in 24 bits so that the range is [–1 to 0.9999999]. In
addition, if 8000H is loaded into both X and Y registers, the
resulting multiplication is considered an illegal operation
as an overflow would result. Positive one cannot be
represented in fractional notation, and the multiplier will
actually yield the result 8000H x 8000H = 8000H (–1 x –1
= –1).
ALU. The ALU has two input ports, one of which is
connected to the output of the 24-bit Accumulator. The
other input is connected to the 24-bit P-Bus, the upper 16
bits of which are connected to the 16-bit D-Bus. A shifter
between the P-Bus and the ALU input port can shift the
data by three bits right, one bit right, one bit left or no shift
(Figure 30).
DDATA
XDATA
16 16
X Register (16) Y Register (16)
Multiplier
P Register (24)
24
24
Shift Unit *
24
MUX
24
* Options:
1 Bit Right
3 Bits Right
No Shift
1 Bit Left
DDATA
Mult. (24) Shift Unit *
24 24
16 24
MUX
* Options:
24 1 Bit Right
3 Bits Right
No Shift
1 Bit Left
24
Arithmetic Logic Unit (ALU)
24
Accumulator (24)
Figure 30. ALU Block Diagram
Figure 29. Multiplier Block Diagram
DS95DSP0101 Q4/95
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