Z89323 Datasheet, PDF (20/61 Pages) Zilog, Inc. – 16-BIT DIGITAL SIGNAL PROCESSORS

PRELIMINARY
FUNCTIONAL DESCRIPTION (Continued)
Z89323/373/393
16-BIT DIGITAL SIGNAL PROCESSORS
Bank 13/Ext 0 (low byte)
D7 D6 D5 D4 D3 D2 D1 D0
CSEL0
CSEL1
CSEL2
SCAN
QUAD
D0
D1
D2
Figure 10. ADCTL Register (Low Byte)
Prescaler Values (bits 7, 6, 5)
D2 D1
D0
Prescaler
(Crystal divided by)
0
0
0
8
0
0
1
16
0
1
0
24
0
1
1
32
1
0
0
40
1
0
1
48
1
1
0
56
1
1
1
64
Note:
The ADC is currently being characterized. Converter errors are estimated
to increase to 2 LSBs (Integral non-linearity), 1 LSB (Differential non-
linearity) and 10 mV (Zero error at 25°C) if the voltage swing on the
reference ladder is decreased to –3V.
Modes (bits 4, 3)
QUAD SCAN
0
0 Convert selected channel 4 times
then stop.
0
1 Convert selected channel then stop.
1
0 Convert 4 channels then stop.
1
1 Convert 4 channels continuously.
Channel Select (bits 2, 1, 0)
CSEL2
CSEL1
CSEL0
0
0
0
0
0
1
0
1
0
0
1
1
Channel
0
1
2
3
Bank 13/Ext 0 (high byte)
D15 D14 D13 D12 D11 D10 D9 D8
ADST0
ADST1
ADIE
ADIT
ADCINT
Reserved
ADE
Figure 11. ADCTL Register (High Byte)
ADE (bit 15). A 0 disables any A/D conversions or
access–ing any ADC registers except writing to ADE bit. A
1 Enables all ADC accesses.
Reserved (bits 14, 13). Reserved for future use.
ADCINT (bit 12). This is the ADC Interrupt bit and is Read
Only. The ADCINT will be reset any time this register is
written.
ADIT (bit 11). This bit selects when to set the ADC Interrupt
if ADIE=1. A value of 0 sets the Interrupt after the first A/D
conversion is complete. A value of 1 sets the Interrupt after
the fourth A/D conversion is complete.
ADIE (bit 10). This is the ADC Interrupt Enable. A value of
0 disables setting the ADC Interrupt. A value of 1 enables
setting the ADC Interrupt.
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DS95DSP0101 Q4/95