Z89323 Datasheet, PDF (16/61 Pages) Zilog, Inc. – 16-BIT DIGITAL SIGNAL PROCESSORS

PRELIMINARY
EXT Register Assignments (Continued)
Ext 7 Reg
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Z89323/373/393
16-BIT DIGITAL SIGNAL PROCESSORS
Bank Select
0000 : Bank0
0001 : Bank1
:
:
1111 : Bank15
Interrupt Status Bits
Bit 4 = A/D Finish Interrupt
Bit 5 = SPI Interrupt
Bit 6 = Timer0 Interrupt
Bit 7 = Timer1 Interrupt
Bit 8 = Timer2 Interrupt
Bit 9 = INT0 (H/W) Interrupt
Bit 10 = INT1 (H/W) Interrupt
Bit 11 = INT2 (H/W) Interrupt
Reserved
Figure 8. EXT7 Register Bit Assignment
Interrupt Status Bits
When read, these bits provide interrupt information to
identify the source for INT2, or when the DSP works in
Pending Interrupt mode, to warn the DSP of pending
interrupts. These bits also clear the interrupt status bits.
Writing 1 will clear these bits.
Wait-State Register
The Wait-State Control Register enables insertion of Wait
States when the DSP needs to access slow, inexpensive
peripherals. This software-controlled register enables
insertion of one Wait State when accessing EXT bus. (One
Wait State gives 100 nsec access time instead of 50 nsec
access time with a 20 MHz oscillator.) When more than one
Wait State is needed, an input pin (WAIT) coupled with
external logic can support more than one Wait State. The
Wait-State Control Register enables mapping specific EXT
register (from EXT0 to EXT6) and specific operation (read
or write) to include insertion of one Wait State. EXT7 is
always internal register, therefore no Wait State is needed
for EXT7.
Note:
When the programmer switches banks it is important to change the Wait
State mapping of the EXT registers to match the desired Wait State
mapping of the new bank.
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DS95DSP0101 Q4/95