Z89323 Datasheet, PDF (38/61 Pages) Zilog, Inc. – 16-BIT DIGITAL SIGNAL PROCESSORS

PRELIMINARY
FUNCTIONAL DESCRIPTION (Continued)
Z89323/373/393
16-BIT DIGITAL SIGNAL PROCESSORS
Hardware Stack. A six-level hardware stack is connected
to the D-Bus to hold subroutine return addresses or data.
The Call instruction pushes PC+2 onto the stack, and the
RET instruction pops the contents of the stack to the PC.
User Inputs. The Z89323 has two inputs, UI0 and UI1,
which may be used by Jump and Call instructions. The
Jump or Call tests one of these pins and if appropriate,
jumps to a new location. Otherwise, the instruction behaves
like a NOP. These inputs are also connected to the status
register bits S10 and S11, which may be read by the
appropriate instruction (Figure 8).
User Outputs. The status register bits S5 and S6 connect
directly to UO0 and UO1 pins and may be written to by the
appropriate instruction. Note: The user output value is the
opposite of the status register content.
Interrupts. The Z89323 has three positive edge-triggered
interrupt inputs serving up to eight interrupt sources. An
interrupt is acknowledged at the end of an instruction
execution. It takes two machine cycles to enter an interrupt
instruction sequence. The PC is pushed onto the stack and
Interrupts are globally disabled. A RET instruction transfers
the contents of the stack to the PC and decrements the
stack pointer by one word. The priority of the interrupts is
IINT0 = highest, IINT2 = lowest. Note: The SIEF instruction
globally enables the interrupts. The SIEF instruction must
be used before exiting an interrupt routine since the
interrupts are automatically disabled when entering the
routine. (See Interrupt Controller section for more details.)
Registers. The Z89323 has 28 physical internal registers,
eight external registers and 15 peripheral control registers.
The EA2-EA0 determines the address of the external
registers. The signals are used to read from or write to the
external registers /DS, WAIT, RD//WR.
I/O Bus. The processor provides a 16-bit, CMOS-
compatible bus. I/O Control pins provide convenient
communication capabilities with external peripherals, and
single-cycle access is possible. For slower
communications, an on-board hardware wait-state
generator can be used to accommodate timing conflicts.
Three latched I/O address pins are used to access external
registers. Disabling a peripheral allows access to these
addresses for general-purpose use.
Wait-State Generator. An internal Wait-State generator is
provided to accommodate slow external peripherals. A
single Wait-State can be implemented through a control
register. For additional states, a dedicated pin
(WAIT) can be held High. The WAIT pin is monitored only
during execution of a read or write instruction to external
peripherals (EXT bus).
Analog to Digital Converter. The Z89323 has a 4-channel,
8-bit half-flash analog to digital converter. Two external
reference voltages are available externally. The ADC
prescales to the system clock and can drive an interrupt at
the end of a conversion. There are four channels of input
with the ADC which can be programmed to convert values
either continuously or on an event (timer or interrupt).
Timer/Counter/PWMs (T0, T1). Timer0 and Timer1 are
16-bit timer-counters with 8-bit prescalers. They also offer
the option of being used as PWM generators and have
both hardware and software Watch-Dog capabilities. Both
timers are identical and can be externally or internally
clocked and can drive any of the three hardware interrupts.
Timer/Counter (T2). Timer 2 is a general-purpose 16-bit
timer/counter. It can be externally or internally clocked and
drive either IINT0 and IINT1.
Port 0. Port 0 is a 16-bit user I/O port. Bits can be
configured as input or output or globally as open-drain
output. When enabled, Port 0 consumes the 16 data lines
used by the EXT bus. Port 0 function and EXT use can be
dynamically changed by enabling and disabling Port 0.
Port 1. Port 1 is an 8-bit user I/O port. Bits can be
configured as input or output or globally as open-drain
output.
Port 2. Port 2 has multiple functions. It can be used as an
8-bit user I/O port when the other functions within the port
are not in use. As an I/O port, these bits can be configured
as input or output or globally as open-drain output. Port 2
also supports the SPI, CLKOUT, all three external hardware
interrupt signals and all three timer input and output
signals.
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