Z89323 Datasheet, PDF (34/61 Pages) Zilog, Inc. – 16-BIT DIGITAL SIGNAL PROCESSORS

CLOCK Circuits
PRELIMINARY
Z89323/373/393
16-BIT DIGITAL SIGNAL PROCESSORS
The clock generator includes Phase-Locked Loop (PLL)
circuit to enable use of low frequency crystal. The benefits
of using low frequency crystal are low system cost, low
power consumption and low EMI. The PLL circuit can be
bypass (s/w controlled).
The clock generated by the PLL circuit (VCO clock) is
programmable and controlled by the PLL Divider register.
DSP (System) clock source is programmable and can be
one of the 4 options: VCO clock, VCO clock divided by 2,
VCO clock divided by 4 or twice the crystal frequency.
Whenever the PLL circuit is switched from Stop VCO to
Enable VCO, a software delay of 10 msec must be used
before switching the system clock from the oscillator to the
PLL, in order to give the PLL time to be stable.
Table 12. CLOCK Modes
STOP_OSC
STOP_VCO
BYPASS_PLL
Mode
0
0
0
0
0
1
0
0) Normal - High frequency clock
1
1) 32 Khz - VCO running (fast switching time)**
0
2) STOP CLOCK - Oscillator running
0
1
1
1
1
0
1
1
1
Notes:
* In this clock mode, it is possible to use external clock source instead
of the internal oscillator source.
** Default (power-up) mode of operation.
3) 32 Khz
4) STOP CLOCK
5) EXTERNAL CLOCK source *
32 kHz
Off-Chip On-Chip
LPF
VCO
Phase
Detector
STOP_VCO
:2
8-Bit
Divider
00
:2
01 _MUX
10
11
:2
0
MUX
System
Clock
1
PLL Divider
Clock Source
STOP_OSC
Bank4 / Ext5
BYPASS_PLL
Figure 26. PLL Functional Block Diagram
34
DS95DSP0101 Q4/95