Z89323 Datasheet, PDF (28/61 Pages) Zilog, Inc. – 16-BIT DIGITAL SIGNAL PROCESSORS

PRELIMINARY
TIMER/COUNTERS (Continued)
16-Bit General-Purpose Timer/Counter T2
Z89323/373/393
16-BIT DIGITAL SIGNAL PROCESSORS
The 16-bit timer/counter is available for general-purpose
use. When the counter counts down to the zero state, the
timer 2 load register loads into timer 2, and if timer 2
interrupt is enabled, an interrupt is received. The counting
operation of the counter can be disabled. The timer/
counter clock source can be selected to be system clock/
2 or UI2.
The counter is defaulted to the Enable state. If the system
designer does not choose to use the timer, the counter can
be disabled.
Bank 14/EXT 0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Count Value (Down-Counter)
Figure 18. Timer/Counter 2 Load Register
I/O Ports
I/O pin allocation for ports in the different package types is
designed to provide increased flexibility and support for
various modes of operation. The 44-pin package features
the special signals, as well as all packages supporting the
EXT 16-bit bus. In cases where the application does not
require an external EXT bus, these I/O pins can be allocated
to 16-bit general-purpose I/O port (P0), the special signals
port (P1) or additional port (P3). The 80-pin PQFP package
supports up to 40 I/O pins.
Table 9. Various Package I/O Port Allocation
Pin Count
Package
44-Pin
PLCC/PQFP
68-Pin
PLCC
80-Pin
PQFP
P0[15:8]
P0[7:0]
P1[7:0]
P2[7:0]
P3[7:0]
EXT,P0,P1*
EXT,P0
P2[4:0]*
EXT,P0
EXT,P0
P1*
P2*
Note:
* Ports with special signals: Interrupts inputs, Serial Peripheral Interface
(SPI), CLKOUT and Timers inputs and outputs.
† (ICE chip)
EXT,P0
EXT,P0
P1*
P2*
P3
100-Pin
PQFP^†
EXT,P0
EXT,P0
P1*
P2*
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DS95DSP0101 Q4/95