Z89323 Datasheet, PDF (15/61 Pages) Zilog, Inc. – 16-BIT DIGITAL SIGNAL PROCESSORS

EXT Register Assignments
PRELIMINARY
Z89323/373/393
16-BIT DIGITAL SIGNAL PROCESSORS
The EXT registers support is extended in the Z893X3
family: In addition to up to seven external registers, there
are 28 internal registers on the EXT bus. There are 16
different pages of EXT registers. The same EXT7 register
exist in all the pages and control of the bank switching is
done via EXT7 register.
Banks 0 to 5 support different combinations of external
registers and internal data registers. The user should use
the bank that has the internal data registers and the
number of external registers to support his application and
to use this bank as a working bank to minimize the number
of bank switching. Bank 5 has all the A/D registers. Banks
13 to 15 are control registers bank. These control registers
are usually used only in the initialization routines.
Table 6. EXT Register Assignments Banks 0–4
EXT\Bank
EXT0
EXT1
EXT2
EXT3
EXT4
EXT5
EXT6
EXT7
0
Ext0-user
Ext1-user
Ext2-user
SPI data
Port0
Port1/Port2
A/D_ch0
Bank/Int_status
1
Ext0-user
Ext1-user
Ext2-user
Ext3-user
Port0
Port1/Port2
A/D_ch1
Bank/Int_status
2
Ext0-user
Ext1-user
Ext2-user
Ext3-user
Ext4-user
Port3
A/D_ch2
Bank/Int_status
3
Ext0-user
Ext1-user
Ext2-user
SPI data
Ext4-user
Ext5-user
A/D_ch3
Bank/Int_status
4
Ext0-user
Ext1-user
Ext2-user
Ext3-user
Ext4-user
Ext5-user
Ext6-user
Bank/Int_status
Table 7. EXT Register Assignments Banks 6–15
EXT\Bank
EXT0
EXT1
EXT2
EXT3
EXT4
EXT5
EXT6
EXT7
5
A/D_ch1
A/D_ch2
A/D_ch3
SPI data
Port0
Port1/Port2
A/D_ch0
Bank/Int_status
6-12
A/D_ch0
Bank/Int_status
13
A/D control
Timer0 control
Timer0 load
Timer0
Timer0 pr. load
Timer0 prescaler
A/D_ch0
Bank/Int_status
14
Timer2 load
Timer1 control
Timer1 load
Timer1
Timer1 pr. load
Timer1 prescaler
A/D_ch0
Bank/Int_status
15
P0 control
P1 control
P2 control
Wait State
SPI control
PLL control
Int. Allocation
Bank/Int_status
DS95DSP0101 Q4/95
15