Z89323 Datasheet, PDF (27/61 Pages) Zilog, Inc. – 16-BIT DIGITAL SIGNAL PROCESSORS

Prescaler Operation
PRELIMINARY
Z89323/373/393
16-BIT DIGITAL SIGNAL PROCESSORS
The Timer/Counter Clock (TMCLK) is generated by the
output of the prescaler. The Prescaler is an 8-bit down
counter, TPR, followed by a divide-by-two flip-flop that
generates a 50 percent duty cycle output clock TMCLK.
The Prescaler’s input clock is the system clock, CLKIN,
divided by two. Thus, the maximum prescaler output
frequency is 1/4 of the system clock frequency.
The 8-bit prescaler counter is loaded with value in TPLR
Register field [7:0] in one of three ways:
1. When 8-bit prescaler counter, TPR,
decrements to zero.
2. By writing to TPR Register.
Once the prescaler counter is loaded, it decrements at its
clocked frequency and generates an output to the divide-
by-two flip-flop. When the count reaches 0, the counter is
reloaded from the lower 8 bits of TPLR Register.
3. When companion Timer/Counter TMR is reloaded
upon under flow from its TMLR Register, or
retriggered by writing directly to TMR Register.
15 14
87
IP
Zeros
Prescaler
Reload Value
0
TPLR
Register
Clock
TPR
DIV
(System Clock)
8-Bit Counter
by 2
Figure 16. Prescaler Block Diagram
15
0
TMLR Register
TMCLK
15
0
UIO
M
U
UI1
X
TMR Register
16-Bit Counter
TMCLK
S
U00
E
L
U01
Figure 17. Counter/Timer Block Diagram
DS95DSP0101 Q4/95
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