Z89323 Datasheet, PDF (11/61 Pages) Zilog, Inc. – 16-BIT DIGITAL SIGNAL PROCESSORS

PIN FUNCTIONS
PRELIMINARY
Z89323/373/393
16-BIT DIGITAL SIGNAL PROCESSORS
CLKO-CLKI Clock (output/input). These pins act as the Priority is: INT2 = lowest, INT0 = highest. (Note: INT2 pin
clock circuit input and output.
is not bonded out on the 44-pin QFP or PLCC packages.)
EXT15-EXT0 External Data Bus (input/output). These pins
act as the data bus for user-defined outside registers, such
as an ADC or DAC. The pins are normally tri-stated, except
when the outside registers are specified as destination
registers in the instructions. All the control signals exist to
allow a read or a write through this bus. If user I/O Port 0
is enabled, these signals function as user Programmable
I/O.
RD//WR Read/Write Strobe (output). This pin controls the
data direction signal for the EXT-Bus. Data is available
from the CPU on EXT15-EXT0 when this signal is Low. EXT-
Bus is in input mode (high-impedance) when this signal is
High.
/RES Reset (input, active Low). This pin controls the
asynchronous reset signal. The /RES signal must be kept
Low for at least one clock cycle (clock output of the PLL
block). The CPU pushes the contents of the Program
Counter (PC) onto the stack and then fetches a new PC
value from program memory address 0FFCH (or FFFCH for
the Z89393) after the reset signal is released.
WAIT WAIT State (input). The wait signal is sampled at the
rising edge of the clock with appropriate setup and hold
times. The normal write cycle will continue when wait is
inactive on a rising clock. A single wait-state can be
generated internally by setting the appropriate bits in the
wait state register (Bank 15/Ext 3) (active high).
EA2-EA0 External Address (output). These pins control
the user-defined register address output (latched). One of
eight user-defined external registers is selected by the
processor with these address pins for read or write
operations. Since the addresses are part of the processor
memory map, the processor is simply executing internal
reads and writes. External Addresses are used internally
by the processor if the ADC, bit I/O (Port 0- 2), or SPI are
enabled. (See the banks allocation of the EXT registers in
Tables 6 and 7.)
P00-P015 Port 0 (input/output). These pins control Port 0
input and output when EXT I/F is not in use.
P10-P17 Port 1 (input/output). These pins are used for
Port 1 programmable bit I/O when INT2, CLKOUT, SPI, or
UI0-1 are not being used.
P20-P27 Port 2 (input/output). These pins control Port 2
input or output when UI2, UO0-2 or INT0-INT1 are not
being used.
/DS Data Strobe (output). This pin control the data strobe
signal for EXT-Bus. Data is read by the external peripheral
on the rising edge of /DS. Data is also read by the
processor on the rising edge of CK.
HALT Halt State (input). This pin controls Stop Execution.
The CPU continuously executes NOPs and the program
counter remains at the same value when this pin is held
High. An interrupt request must be executed (enabled) to
exit HALT mode. After the interrupt service routine, the
program continues from the instruction after the HALT
(active high).
/INT0-/INT2 Three Interrupts (input, active on rising edge).
These pins control interrupt requests 0-2. Interrupts are
generated on the rising edge of the input signal. Interrupt
vectors for the interrupt service starting address are stored
in the following program memory locations:
Device
Z89323/373
Z89393
/INT0
1FFFH
FFFFH
/INT1
1FFEH
FFFEH
/INT2
1FFDH
FFFDH
P30-P37 Port 3 Port3 (3:0) are four inputs and P3 (7:0) are
four outputs.
UI1-UI0 Two Input Pins (input). These general-purpose
input pins are directly tested by the conditional branch
instructions. These are asynchronous input signals that
have no special clock synchronization requirements.
UO1-UO0 Two Output Pins (output). These general-
purpose output pins reflect the value of two bits in the
status register S5 and S6. These bits have no special
significance and may be used to output data by writing to
the status register. Note: The user output value is the
opposite of the status register content.
SIN/SOUT. When enabled, these pins control SPI input
and output.
AN0-AN3. These pins are used for Analog-to-Digital
converter input.
ANGND and ANVCC. Analog to Digital ground and power
supply.
DS95DSP0101 Q4/95
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