Z89323 Datasheet, PDF (33/61 Pages) Zilog, Inc. – 16-BIT DIGITAL SIGNAL PROCESSORS

PRELIMINARY
Z89323/373/393
16-BIT DIGITAL SIGNAL PROCESSORS
When the communication between the master and slave is
complete, the SS goes High. Unless disconnected, for
every bit that is transferred into the slave through the SIN
pin, a bit is transferred out through the SOUT pin on the
opposite clock edge. During slave operation, the SPI clock
pin (SK) is an input (Figure 25). In master mode, the DSP
must first activate a SS through one of it’s I/O ports. Next,
data is transferred through the master’s SOUT pin one bit
per master clock cycle. Loading data into the shift register
initiates the transfer. In master mode, the master’s clock
drives the slave’s clock. At the conclusion of a transfer, a
Receive Character Available SPI interrupt and flag is
generated. Before data is transferred through the SOUT
pin, the SPI Enable bit in the SCON Register must be
enabled. The MSB bit 7 is shifted out first.
SPI Clock. The SPI clock can be driven from three sources;
with T0, a division of the internal system clock, or an
external master when in slave mode. Bit D6 of the SCON
Register controls what source drives the SPI clock. Divided
by 2, 4, 8, or 16 can be chosen as the scaler with bits D2,
D1 in master mode.
Receive Character Available and Overrun. When a
complete data stream is received an interrupt is generated
and the RxCharAvail bit in the SCON Register is set. The
SPI interrupt can be enabled or disabled (default) in the
Interrupt Allocation Register (Bank 15/Ext 6). The
RxCharAvail bit is available for interrupt polling purposes
and is reset when the RxBUF Register is read. RxCharAvail
is generated in both master and slave modes. While in
slave mode, if the RxBUF is not read before the next data
stream is received and loaded into the RxBUF Register,
Receive Character Overrun (RxCharOverrun) occurs. Since
there is no need for clock control in slave mode, bit D1 in
the SPI Control Register is used to log any RxCharOverrun.
SK
(Input/Output
Input
(Active Low)
SS
SOUT
SIN
3
4
2
1
5
Figure 25. SPI Timing
DS95DSP0101 Q4/95
33