Z89323 Datasheet, PDF (49/61 Pages) Zilog, Inc. – 16-BIT DIGITAL SIGNAL PROCESSORS

PRELIMINARY
Inst. Description
SCF SetCflag
SIEF SetIEflag
SLL Shiftleft
logical
SOPF SetOPflag
SRA Shiftright
arithmetic
SUB Subtract
Synopsis
SCF
SIEF
SLL
SOPF
SRA<cc>,A
SUB<dest>,<src>
XOR BitwiseexclusiveOR XOR<dest>,<src>
Operands
None
None
[<cc>,]A
A
None
<cc>,A
A
A,<pregs>
A,<dregs>
A,<limm>
A, <memind>
A, <direct>
A, <regind>
A, <hwregs>
A, <simm>
A, <pregs>
A, <dregs>
A, <limm>
A, <memind>
A, <direct>
A, <regind>
A, <hwregs>
A, <simm>
Words
1
1
1
1
1
1
1
1
1
2
1
1
1
1
1
1
2
1
1
1
1
Z89323/373/393
16-BIT DIGITAL SIGNAL PROCESSORS
Cycles
1
1
1
1
1
1
1
1
1
2
3
1
1
1
1
1
2
3
1
1
1
Examples
SCF
SIEF
SLL NZ,A
SLL A
SOPF
SRANZ,A
SRAA
SUB A,P1:1
SUB A,D0:1
SUB A,#%2C2C
SUB A,@D0:1
SUB A,%15
SUB A,@P2:0–LOOP
SUBA,STACK
SUB A, #%12
XOR A,P2:0
XOR A,D0:1
XOR A,#13933
XORA,@@P2:1+
XORA,%2F
XORA,@P2:0
XORA,BUS
XOR A, #%12
Bank Switch Enumerations. The third (optional) operand
of the MLD, MPYA and MPYS instructions represents
whether a bank switch is set ON or OFF. To more clearly
represent this, the keywords ON and OFF are used to state
the direction of the switch. These keywords are referenced
in the instruction descriptions through the <bank switch>
symbol. The most notable capability this provides is that a
source operand can be multiplied by itself (squared).
DS95DSP0101 Q4/95
49