Z89323 Datasheet, PDF (36/61 Pages) Zilog, Inc. – 16-BIT DIGITAL SIGNAL PROCESSORS

Interrupt Controller
PRELIMINARY
Z89323/373/393
16-BIT DIGITAL SIGNAL PROCESSORS
There are eight different interrupt sources (when all of them
are enabled). Bits [3:0] of the Interrupt Allocation Register
defines which interrupt source will have the highest priority
and will be allocated into IINT0 (Internal INT0). Bits[7:0] of
the Interrupt Allocation Register defines which interrupt
source will have the second highest priority and will be
allocated into IINT1 (Internal INT1). Bits[15:8] are enable
bits for specific interrupt sources. All the enabled interrupts
which are not already allocated into IINT0 or IINT1 are
allocated into IINT2. When interrupt happen on IINT2 then
IINT2 interrupt routine is reading the Interrupt Status Register
(EXT7 in all the Banks) to determine which interrupt occurred
and decides on the relative priority. The Interrupt Status
Register can be used for polling interrupts mode.
Bank 15/Ext 6 Reg
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Note: An Interrupt that is not selected as a source to IINT0, IINT1 or IINT2 is disabled.
IINT0 Source
0000 : A/D Finish 0001 : SPI
0010 : Timer0
0011 : Timer1
0100 : Timer2
0101 : INT0 H/W
0110 : INT1 H/W 0111 : INT2 H/W
1000 – 1111 : IINT0 Disabled
IINT1 Source
0000 : A/D Finish 0001 : SPI
0010 : Timer0
0011 : Timer1
0100 : Timer2
0101 : INT0 H/W
0110 : INT1 H/W 0111 : INT2 H/W
1000 – 1111 : IINT1 Disabled
IINT2 Interrupt Sources
Interrupt Interrupt
Enable Disable
Bit 8 = A/D Finish 1
0
Bit 9 = SPI
1
0
Bit 10 = Timer0 1
0
Bit 11 = Timer1 1
0
Bit 12 = Timer2 1
0
Bit 13 = INT0 H/W 1
0
Bit 14 = INT1 H/W 1
0
Bit 15 = INT2 H/W 1
0
Figure 28. Interrupt Allocation Register
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DS95DSP0101 Q4/95