Z89323 Datasheet, PDF (21/61 Pages) Zilog, Inc. – 16-BIT DIGITAL SIGNAL PROCESSORS

PRELIMINARY
Z89323/373/393
16-BIT DIGITAL SIGNAL PROCESSORS
START (bits 9, 8)
ADST1 ADST0
0
0
0
1
1
0
1
1
Mode
Conversion starts when
this register is written.
Conversion starts on a
rising edge INT1 input pin.
Conversion starts when
Timer 2 times out.
Conversion starts when
Timer 0 times out.
There are four ADC result registers. For their location in the
different banks, see EXT Register Assignments.
Figure 12 shows the input circuit of the ADC. When
conversion starts, the analog input voltage from one of the
eight channel inputs is connected to the MSB and LSB
flash converter inputs as shown in the Input Impedance
CKT diagram. This effectively shunts 31 parallel internal
resistance of the analog switches and simultaneously
charges 31 parallel 0.5 pF capacitors, which is equivalent
to seeing a 400 Ohms input impedance in parallel with a
16 pF capacitor. Other input stray capacitance adds about
10 pF to the input load. For input source, resistances up to
2 kOhms can be used under normal operating conditions
without any degradation of the input settling time. For
larger input source resistance longer conversion cycle
time may be required to compensate the input settling time
factor.
CMOS Switch
on Resistance
2-5kΩ
R Source
C Parasitic
V Ref
V Ref
V Ref
C .5 pF
C .5 pF
C .5 pF
Figure 12. Input Impedance of ADC
31 CMOS Digital
Comparators
DS95DSP0101 Q4/95
21