Z89323 Datasheet, PDF (47/61 Pages) Zilog, Inc. – 16-BIT DIGITAL SIGNAL PROCESSORS

PRELIMINARY
Z89323/373/393
16-BIT DIGITAL SIGNAL PROCESSORS
Inst. Description Synopsis
LD
Loaddestination LD<dest>,<src>
with source
MLD Multiply
MLD<srcl>,<srcl>[,<bank switch>]
Operands
A,<hwregs>
A,<dregs>
A,<pregs>
A,<regind>
A,<memind>
A,<direct>
<direct>,A
<dregs>,<hwregs>
<pregs>,<simm>
<pregs>,<hwregs>
<regind>,<limm>
<regind>,<hwregs>
<hwregs>,<pregs>
<hwregs>,<dregs>
<hwregs>,<limm>
<hwregs>,<accind>
<hwregs>,<memind>
<hwregs>,<regind>
<hwregs>,<hwregs>
Words Cycles Examples
1 1 LDA,X
1 1 LDA,D0:0
1 1 LDA,P0:1
1 1 LDA,@P1:1
1 3 LDA,@D0:0
1 1 LDA,124
1 1 LD124,A
1 1 LDD0:0,EXT7
1 1 LDP1:1,#%FA
1 1 LDP1:1,EXT1
1 1 LD@P1:1,#1234
1 1 LD@P1:1+,X
1 1 LDY,P0:0
1 1 LDSR,D0:0
2 2 LDPC,#%1234
1 3 LDX,@A
1 3 LDY,@D0:0
1 1 LDA,@P0:0–LOOP
1 1 LDX,EXT6
Note: When<dest>is<hwregs>,<dest>cannotbeP.
Note: When<dest>is<hwregs>and<src>is<hwregs>,<dest>cannotbeEXTn
if <src> is EXTn, <dest> cannot be X if <src> is X, <dest> cannot be SR
if <src> is SR.
Note: When<src>is<accind><dest>cannotbeA.
<hwregs>,<regind>
1 1 MLDA,@P0:0+LOOP
<hwregs>,<regind>,<bankswitch> 1 1 MLDA,@P1:0,OFF
<regind>,<regind>
1 1 MLD@P1:1,@P2:0
<regind>,<regind>,<bankswitch> 1 1 MLD@P0:1,@P1:0,ON
Note: Ifsrc1is<regind>itmustbeabank1register.Src2’s<regindmustbe
a bank 0 register.
Note: <hwregs>forsrc1cannotbeX.
Note: Fortheoperands<hwregs>,<regind>the<bandswitch>defaultstoOFF.
For the operands <regind>, the <bank switch> defaults to ON.
MPYA
Multiply and add
MPYA <srcl>,<src2>[,<bank switch>]
<hwregs>,<regind>
1
<hwregs>,<regind>,<bankswitch> 1
<regind>,<regind>
1
<regind>,<regind>,<bankswitch> 1
1 MPYAA,@P0:0
1 MPYAA,@P1:0,OFF
1 MPYA@P1:1,@P2:0
1 MPYA@P0:1,@P1:0,ON
Note: Ifsrc1is<regind>itmustbeabank1register.Src2’s<regind>mustbe
a bank 0 register.
Note: <hwregs>forsrc1cannotbeX.
Note: Fortheoperands<hwregs>,<regind>the<bankswitch>defaultstoOFF.
For the operands <regind>, the <bank switch> defaults to ON.
DS95DSP0101 Q4/95
47