Z89323 Datasheet, PDF (18/61 Pages) Zilog, Inc. – 16-BIT DIGITAL SIGNAL PROCESSORS

FUNCTIONAL DESCRIPTION
PRELIMINARY
Z89323/373/393
16-BIT DIGITAL SIGNAL PROCESSORS
Analog to Digital Converter (ADC)
The ADC is an 8-bit half flash converter that uses two
reference resistor ladders for its upper 4 bits (Most
Significant Bits) and lower 4 bits (Least Significant Bits)
conversion. Two reference voltage pins, VA (High) and VA
(Low), are provided for external reference voltage supplies.
During the sampling period from one of the four channel
inputs, the converter is also being auto-zeroed before
starting the conversion. The conversion time is dependent
on the external clock frequency and the selection of the
prescaler value for the internal ADC clock source. The
minimum conversion time is 2.0 µs. (See Figure 9, ADC
Architecture.)
The ADC control register is Bank 13/Ext 0. A conversion
can be initiated in one of four ways: by writing to the
A/D control register, INT1 input pin, Timer 2 or Timer 0
equal 0. These four are programmable selectable. There
are four modes of operation that can be selected: one
channel converted four times with the results written to
each Result register, one channel continuously converted
and one Result channel updated for each conversion, four
channels converted once each and the four results written
to the Result registers, and four channels repeatedly
converted and the Result registers kept updated. The
channel to be converted is programmable and if one of the
four-channel modes is selected then the programmed
channel will be the first channel converted and the other
three will be in sequence following with wraparound from
Channel 3 to Channel 0.
The start commands are implemented in such a way as to
begin a conversion at any time, if a conversion is in
progress and a new start command is received, then the
conversion in progress will be aborted and a new conversion
will be initiated. This allows the programmed values to be
changed without affecting a conversion-in-progress. The
new values will take effect only after a new start command
is received.
The clock prescaler can be programmed to derive a
minimum 2 µs conversion time for clock inputs from 4 MHz
to 20 MHz. For example, with a 20 MHz crystal clock the
prescaler should be programmed for divide by 40, which
then gives a 2 µs conversion rate.
The ADC can generate an Interrupt after either the first or
fourth conversion is complete depending on the
programmable selection.
The ADC can be disabled (for low power) or enabled by a
Control Register bit.
Though the ADC will function for a smaller input voltage
and voltage reference, the noise and offsets remain constant
during the specified electrical range. The errors of the
converter will increase and the conversion time may also
take slightly longer due to smaller input signals.
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DS95DSP0101 Q4/95