Z89323 Datasheet, PDF (24/61 Pages) Zilog, Inc. – 16-BIT DIGITAL SIGNAL PROCESSORS

PRELIMINARY
TIMER/COUNTERS (Continued)
Z89323/373/393
16-BIT DIGITAL SIGNAL PROCESSORS
Timer Modes
The Timer modes can be categorized as input modes and
output modes. In input modes, the Timer/Counter is used
for input signals only. In output modes, a selected output
pin is driven. If a Timer/Counter is enabled (CE=1) and an
output pin, UO0 or UO1, is selected to be driven, the DSP
Processor’s Status Register bits 5 or 6 does not affect the
state of that pin.
Output Modes
MODE 0. The Timer/Counter is configured to generate a
continuous square wave of 50% duty cycle. Writing a new
value to the TMLR Register takes effect at the end of
current cycle unless TMR is written.
MODE 5. The Timer/Counter is configured to generate an
output pulse that is asserted under program control, and
de-asserted when a programmable number of input edges
(up to 65,535) have been counted on an input pin (UI0 or
UI1). Assertion may be either logic high or logic low.
MODE 6. The Timer/Counter is configured to generate a
Hardware Reset on time-out unless retriggered by software.
MODE 7. The Timer/Counter is configured to generate a
Hardware Reset on time-out unless retriggered by an
event on one of the input pins UI0 or UI1.
Input Modes
MODE 1. The Timer/Counter is configured to generate a
single pulse of programmable duration. The asserted state
may be either logic high or logic low. Retriggering the one-
shot before the end of the pulse causes it to continue for the
new duration.
The input modes use one of the input pins UI0 or UI1. The
signals on these pins are synchronized with the internal
Timer Clock, TMCLK, before being applied to the Timer.
The input signal frequency must be no higher than 1/4th of
TMCLK frequency.
MODE 2. The Timer/Counter is configured to generate a
pulse-width modulated repeating waveform. The duty cycle
ranges from 0–100% (0/256 to 255/256) of a cycle in steps
of 1/256 of a cycle. The asserted state of the waveform may
be either logic high or logic low. Writing a new pulse-width
value to the TMLR Register takes effect at the end of
current cycle unless TMR is written.
MODE 3. The Timer/Counter is configured to generate a
pulse-width modulated repeating waveform. The duty cycle
ranges from 0–100% (0/65,536 to 65,535/65,536) of a
cycle in steps of 1/65,536 of a cycle. The asserted state of
the waveform may be either logic high or logic low. Writing
a new pulse-width value to the TMLR Register takes effect
at the end of current cycle unless TMR is written.
MODE 4. The Timer/Counter is configured to generate a
series of pulses ranging from 0 to 65,535. The pulses are
actually the Timer Clock (TMCLK), which is gated to the
output until the counter under flows.
MODE 8. The Timer/Counter is configured to measure the
time for which its input is asserted.
MODE 9. The Timer/Counter is configured to measure the
period from one rising (falling) edge to the next rising
(falling) edge on the input.
MODE 10. The Timer/Counter is configured to count the
number of input edges (up to 65,535). Input edges may be
selected as rising or falling or both.
MODE 11. The Timer/Counter is configured to count the
number of input edges (up to 65,535) in a time window set
by the second timer. Edges are counted until the second
timer under flows. Input edges may be selected as rising
or falling or both.
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DS95DSP0101 Q4/95