Z89323 Datasheet, PDF (32/61 Pages) Zilog, Inc. – 16-BIT DIGITAL SIGNAL PROCESSORS

Serial Peripheral Interface
PRELIMINARY
Z89323/373/393
16-BIT DIGITAL SIGNAL PROCESSORS
Serial Peripheral Interface (SPI). The Z893X3 incorporates
a serial peripheral interface for communication with other
microcontrollers and peripherals. The SPI includes features
such as Master/Slave selection. The SPI consists of two
registers; SPI Control Register (SCON), SPI Receive/Buffer
Register (RxBUF), and SPI Shift Register (Figure 23). Note:
The SPI shift register and Receive/Buffer register are one
in the same and are shown in Figure 41. SCON is located
in bank 15/Ext4 (LSB). This register is a read/write register
that controls; Master/Slave selection, SS polarity, clock
source and phase selection, and error flag. Bit 0 enables/
disables the SPI with the default being SPI disabled. A 1 in
this location enables the SPI, and a 0 disables the SPI.
Bits 1 and 2 of the SCON register in Master Mode selects
the clock rate. The user may choose whether internal clock
is divide by 2, 4, 8, or 16. In Slave Mode, Bit 1 of this register
flags the user if an overrun of the RxBUF Register has
occurred.
The RxCharOverrun flag can only be reset by writing a 0 to
this bit. In slave mode, bit 2 of the Control Register can
disable the data-out I/O function. If a 1 is written to this bit,
the data-out pin is tri-stated. If a 0 is written to this bit, the
SPI will shift out one bit for each bit received. Bit 3 of the
SCON Register is the SS polarity bit. A 0 selects active Low
(default) polarity on SS, and a 1 selects active High. Bit 4
signals that a receive character is available in the RxBUF
Register. If the associated interrupt enable bit is enabled,
an interrupt is generated. Bit 5 controls the clock phase of
the SPI. A 1 in Bit 5 allows for receiving data on the clock’s
falling edge and transmitting data on the clock’s rising
edge. A 0 allows receiving data on the clock’s rising edge
and transmitting on the clock’s falling edge.
The SPI clock source is defined in bit 6 for Master mode.
A 1 uses Timer0 output for the SPI clock, and a 0 uses a
division of the internal system clock for clocking the SPI. Bit
7 determines whether the SPI is used as a Master or a
Slave. A 1 puts the SPI into Master mode and a 0 puts the
SPI into Slave mode.
slave’s SPI Shift Register, through the SIN pin, which has
the same address as the RxBUF Register. After a byte of
data has been received by the SPI Shift Register a Receive
Character Available SPI interrupt and flag is generated.
The next byte of data may be received at this time, but the
RxBUF Register must be cleared, or a Receive Character
Overrun (RxCharOverrun) flag is set in the SCON Register
and the data in the RxBUF Register is overwritten.
Bank15/Ext4 (LSB) Reg
D7 D6 D5 D4 D3 D2 D1 D0
SPI Enable
1 Enable
2 Disable
Receive Character Overrun (Slave)
Clock Frequency (Master)
0 0 Divide-by-2
0 1 Divide-by-4
1 0 Divide-by-8
1 1 Divide-by-16
DOP (Slave)
0 Enable SOUT as Output
1 Tri-State SOUT
SSP = SS Polarity (Master)
0 = SS Active Low (default)
1 = SS Active High
Received Character Available
CLKP
0 is Transmit on Falling
Receive Data on Rising Edge
1 is Transmit on Rising
Receive Data on Falling Edge
SPI Clock Source Select (Master)
0 is Internal Clock
1 is Timer 0
1 Master 0 Slave
Figure 23. SPI Control Register (SCON)
Bank 0/Ext 3 (LSB) Reg
D7 D6 D5 D4 D3 D2 D1 D0
Figure 24. SPI TXRXDATA Register
SPI Operation. The SPI can be used in one of two modes;
either as system slave, or a system master. In the slave
mode, data transfer starts when the slave select
(SLAVESEL) pin goes Low. Data is transferred into the
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DS95DSP0101 Q4/95