Z89323 Datasheet, PDF (30/61 Pages) Zilog, Inc. – 16-BIT DIGITAL SIGNAL PROCESSORS

PRELIMINARY
8-Bit Programmable I/O (Port 1)
Z89323/373/393
16-BIT DIGITAL SIGNAL PROCESSORS
When the appropriate bit is set in the Port 1 control register,
Port 1 acts as an 8-bit programmable, bi-directional,
CMOS-compatible port. Each of the eight lines can be
independently programmed as an input or an output or
globally as an open-drain output. When enabled,
Bank0/EXT5 (Least Significant Bit) acts as the data I/O
register. Bank15/EXT1 serves as the Port1 direction control
register. Port 1 can also be programmed to provide special
I/O functions.
Port.Bit
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
Table 10. Port 1 Bit Function Selection
IF (Condition Explanation)
Then
Bank15/Ext1(3)=1 (Enable External Interrupt Source INT2)
Bank15/Ext1(5)=1 (CLKOUT Enable)
Bank15/Ext4(0)=1 (SPI Enable)
Bank15/Ext4(0)=1 (SPI Enable)
INT2
CLKOUT
SIN
SOUT
Bank15/Ext4(0)=1 (SPI Enable)
SS
Bank15/Ext4(0)=1 (SPI Enable)
SK
Bank13/Ext1(2-1)=10 or Bank14/Ext1(2-1)=10 (UI0 Enable)
UI0
Bank13/Ext1(2-1)=11 or Bank14/Ext1(2-1)=11 (UI0 Enable)
UI1
Else
P10
P11
P12
P13
P14
P15
P16
P17
Bank 15/Ext 1 Reg
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Pins P0 15-0 Port Allocation
000 : Ext 15-0 (default)
001 : P0 15-8 <= P1 7-0,
P0 7-0 <= Ext 7-0
010 : Reserved
011 : P0 15-8 <= P0 15-8,
P0 7-0 <= Ext 7-0
100 : P0 15-0
101 : P0 15-8 <= P1 7-0
P0 7-0 <= P0 7-0
110 : Reserved
111 : Reserved
1 : Enable External Interrupt Source INT2
0 : Disable External Interrupt Source (default)
1 : Enable External Interrupt Source INT1
0 : Disable External Interrupt Source (default)
1 : CLKOUT Enabled (P11)
0 : CLKOUT Disabled (default)
1 : Port 1 Outputs Open-Drain
0 : Port 1 Outputs Push-Pull (default)
1 : Port 0 Outputs Open-Drain
0 : Port 0 Outputs Push-Pull (default)
Port 1 I/O Directions
1 : Output
0 : Input (default)
Figure 21. Bank15/EXT1 Register
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DS95DSP0101 Q4/95