W83977F-A Datasheet, PDF (93/182 Pages) Winbond – WINBOND I/O

W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A
8.2.5 EPP Data Port 0-3
These four registers are available only in EPP mode. Bit definitions of each data port are as follows:
76 5 4 3 2 1 0
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
When accesses are made to any EPP data port, the contents of DB0-DB7 are buffered (non-inverting)
and output to the ports PD0-PD7 during a write operation. The leading edge of IOW causes an EPP
data write cycle to be performed, and the trailing edge of IOW latches the data for the duration of the
EPP write cycle.
During a read operation, ports PD0-PD7 are read, and the leading edge of IOR causes an EPP read
cycle to be performed and the data to be output to the host CPU.
8.2.6 Bit Map of Parallel Port and EPP Registers
REGISTER
Data Port (R/W)
Status Buffer (Read)
Control Swapper
(Read)
7
PD7
BUSY
1
6
5
PD6 PD5
ACK ^PE
4
PD4
SLCT
1
1 IRQEN
3
PD3
ERROR
SLIN
2
PD2
1
INIT
1
0
PD1
PD0
1
TMOUT
AUTOFD STROBE
Control Latch (Write)
1
1 DIR IRQ
SLIN
INIT AUTOFD STROBE
EPP Address Port
PD7 PD6 PD5 PD4
PD3
PD2
PD1
PD0
R/W)
EPP Data Port 0
(R/W)
PD7 PD6 PD5 PD4
PD3
PD2
PD1
PD0
EPP Data Port 1
(R/W)
PD7 PD6 PD5 PD4
PD3
PD2
PD1
PD0
EPP Data Port 2
(R/W)
PD7 PD6 PD5 PD4
PD3
PD2
PD1
PD0
EPP Data Port 3
(R/W)
PD7 PD6 PD5 PD4
PD3
PD2
PD1
PD0
Publication Release Date: May 2006
-85 -
Revision 0.60