W83977F-A Datasheet, PDF (75/182 Pages) Winbond – WINBOND I/O

W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A
7.7.2 Set5.Reg2 - Flow Control Mode Operation (FC_MD)
These registers control flow control mode operation as shown in the following table.
REG.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
FC_MD FC_MD2 FC_MD1 FC_MD0
-
FC_DSW EN_FD EN_BRFC
Reset
0
0
0
0
0
0
0
Value
BIT 0
EN_FC
0
Bit 7~5
Bit 4:
Bit 3:
FC_MD2 - Flow Control Mode
When flow control is enforced, these bits will be loaded into AD_MD2~0 of advanced
HSR (Handshake Status Register). These three bits are defined as same as AD_MD2~0.
Reserved, write 0.
FC_DSW - Flow Control DMA Channel Swap
A write to 1 allow user to swap DMA channel for transmitter or receiver when flow control
is enforced.
FC_DSW
0
1
Next Mode After Flow Control Occurred
Receiver Channel
Transmitter Channel
Bit 2:
Bit 1:
Bit 0:
EN_FD - Enable Flow DMA Control
A write to 1 enables UART to use DMA channel when flow control is enforced.
EN_BRFC - Enable Baud Rate Flow Control
A write to 1 enables FC_BLL/FC_BHL (Flow Control Baud Rate Divider Latch, in
Set5.Reg1~0) to be loaded into advanced baud rate divisor latch (ADBLL/ADBHL, in
Set2.Reg1~0).
EN_FC - Enable Flow Control
A write to 1 enables flow control function and bit 7~1 of this register.
Publication Release Date: May 2006
-67 -
Revision 0.60