W83977F-A Datasheet, PDF (67/182 Pages) Winbond – WINBOND I/O

W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A
7.3 Set1 - Legacy Baud Rate Divisor Register
ADDRESS
OFFSET
0
1
2
3
4
5
6
7
REGISTER
NAME
BLL
BHL
ISR/UFR
UCR/SSR
HCR
USR
HSR
UDR/ESCR
REGISTER DESCRIPTION
Baud Rate Divisor Latch (Low Byte)
Baud Rate Divisor Latch (High Byte)
Interrupt Status or IR FIFO Control Register
IR Control or Sets Select Register
Handshake Control Register
IR Status Register
Handshake Status Register
User Defined Register
7.3.1 Set1.Reg0~1 - Baud Rate Divisor Latch (BLL/BHL)
These two registers of BLL and BHL are baud rate divisor latch in the legacy SIR/ASK-IR mode.
Accessing these registers in Advanced IR mode will cause backward operation, that is, UART will fall
back to legacy SIR mode and clear some register values as shown in the following table.
SET & REGISTER
ADVANCED MODE
DIS_BACK=¡Ñ
LEGACY MODE
DIS_BACK=0
Set 0.Reg 4
Set 2.Reg 2
Set 4.Reg 3
Bit 7~5
Bit 0, 5, 7
Bit 2, 3
-
Bit 5, 7
-
Note that DIS_BACK=1 (Disable Backward operation) in legacy SIR/ASK-IR mode will not affect any register which is
meaningful in legacy SIR/ASK-IR.
7.3.2 Set1.Reg 2~7
These registers are defined as the same as Set 0 registers.
7.4 Set2 - Interrupt Status or IR FIFO Control Register (ISR/UFR)
These registers are only used in advanced modes.
ADDRESS
OFFSET
REGISTER
NAME
REGISTER DESCRIPTION
0
ABLL
Advanced Baud Rate Divisor Latch (Low Byte)
1
ABHL
Advanced Baud Rate Divisor Latch (High Byte)
2
ADCR1
Advanced IR Control Register 1
3
SSR
Sets Select Register
4
ADCR2
Advanced IR Control Register 2
5
Reserved
-
6
TXFDTH
Transmitter FIFO Depth
7
RXFDTH
Receiver FIFO Depth
Publication Release Date: May 2006
-59 -
Revision 0.60