W83977F-A Datasheet, PDF (68/182 Pages) Winbond – WINBOND I/O

W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A
7.4.1 Reg0, 1 - Advanced Baud Rate Divisor Latch (ABLL/ABHL)
These two registers are the same as legacy IR baud rate divisor latch in SET 1.Reg0~1. In advanced
SIR/ASK-IR mode, user should program these registers to set baud rate. This is to prevent backward
operation from occurring.
7.4.2 Reg2 - Advanced IR Control Register 1 (ADCR1)
MODE
BIT 7 BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
Advanced IR BR_OUT
-
EN_LOUT ALOOP D_CHSW DMATHL
Reset Value
0
0
0
0
0
0
BIT 1
DMA_F
0
BIT 0
ADV_SL
0
Bit 7:
Bit 6:
Bit 5:
Bit 4:
Bit 3:
Bit 2:
BR_OUT - Baud Rate Clock Output
When written to 1, the programmed baud rate clock will be output to DTR pin. This bit is
only used to test baud rate divisor.
Reserved, write 0.
EN_LOUT - Enable Loopback Output
A write to 1 will enable transmitter to output data to IRTX pin when loopback operation.
Internal data can be verified through an output pin by setting this bit.
ALOOP - All Mode Loopback
A write to 1 will enable loopback in all modes.
D_CHSW - DMA TX/RX Channel Swap
If only one DMA channel operates in MIR/FIR mode, then the DMA channel can be
swapped.
D_CHSW
DMA Channel Selected
0
Receiver (Default)
1
Transmitter
A write to 1 will enable output data when ALOOP=1.
DMATHL - DMA Threshold Level
Set DMA threshold level as shown in the following table.
DMATHL
0
1
TX FIFO THRESHOLD
16-BYTE
32-BYTE
13
13
23
7
RX FIFO THRESHOLD
(16/32-BYTE)
4
10
-60